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Publications of Author

1. Haruhisa Hasegawa, Naoaki Yamanaka, Kohei Shiomoto
   Rate Control for High-Speed Burst Transmission with Quick Response in Universal ATM-WAN, ALPEN. [Citation Graph (0, 0)][DBLP]
   ICC (3), 1997, pp:1734-1738 [Conf]
   
2. Yutaka Arakawa, Naoaki Yamanaka, Iwao Sasase
   Performance of Optical Burst Switched WDM Ring Network with TTFR System. [Citation Graph (0, 0)][DBLP]
   OpNeTec, 2004, pp:95-102 [Conf]
   
3. Takanori Ito, Daisuke Ishii, Kohei Okazaki, Naoaki Yamanaka, Iwao Sasase
   A Scheduling Algorithm for Reducing Unused Timeslots by Considering Head Gap and Tail Gap in Time Sliced Optical Burst Switched Networks. [Citation Graph (0, 0)][DBLP]
   OpNeTec, 2004, pp:79-86 [Conf]
   
4. Kohei Shiomoto, Naoaki Yamanaka, Tatsuro Takahashi
   Overview of Measurement-Based Connection Admission Control Methods in ATM Networks. [Citation Graph (0, 0)][DBLP]
   IEEE Communications Surveys and Tutorials, 1999, v:2, n:1, pp:- [Journal]
   
5. Eiji Oki, Naoaki Yamanaka
   Impact of Multimedia Traffic Characteristics on ATM Network Configuration. [Citation Graph (0, 0)][DBLP]
   J. Network Syst. Manage., 1998, v:6, n:4, pp:- [Journal]
   
6. Kouichi Genda, Naoaki Yamanaka
   TORUS: Terabit-per-Second ATM Switching System Architecture Based on Distributed Internal Speed-Up ATM Switch. [Citation Graph (0, 0)][DBLP]
   IEEE Journal on Selected Areas in Communications, 1997, v:15, n:5, pp:817-829 [Journal]
   
7. Shiro Kikuchi, Naoaki Yamanaka
   An Expandable Time-Division Circuit Switching LSI and Network Architecture for Broadband ISDN. [Citation Graph (0, 0)][DBLP]
   IEEE Journal on Selected Areas in Communications, 1996, v:14, n:2, pp:328-336 [Journal]
   
8. Naoaki Yamanaka, Shiro Kikuchi, Masao Suzuki, Yukiharu Yoshioka
   A 2 Gb/s Expandable Space-Division Switching LSI and Network Architecture for Gigabit-Rate Broad-Band Circuit Switching. [Citation Graph (0, 0)][DBLP]
   IEEE Journal on Selected Areas in Communications, 1990, v:8, n:8, pp:1543-1550 [Journal]
   
9. Naoaki Yamanaka, Masaharu Sasaki, Shiro Kikuchi, Thoru Takada, Masao Idda
   A Gigabit-Rate Five-Highway GaAs OE-LSI Chipset for High-Speed Optical Interconnections Between Modules or VLSI's. [Citation Graph (0, 0)][DBLP]
   IEEE Journal on Selected Areas in Communications, 1991, v:9, n:5, pp:689-697 [Journal]
   
10. Kohei Shiomoto, Shinichiro Chaki, Naoaki Yamanaka
    A simple bandwidth management strategy based on measurements of instantaneous virtual path utilization in ATM networks. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 1998, v:6, n:5, pp:625-634 [Journal]
    
11. 
    New Parallel Shortest Path Searching Algorithm based on Dynamically Reconfigurable Processor DAPDNA-2. [Citation Graph (, )][DBLP]
    
    
12. 
    A Deadline-Aware Scheduling Scheme for Wavelength Assignment in l Grid Networks. [Citation Graph (, )][DBLP]
    
    
13. 
    Recover-Forwarding Method in Link Failure with Pre-Established Recovery Table for Wide Area Ethernet. [Citation Graph (, )][DBLP]