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Vishwani D. Agrawal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Vishwani D. Agrawal, Samuel H. C. Poon
    VLSI design process. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer Science, 1985, pp:74-78 [Conf]
  2. Vishwani D. Agrawal, Michael L. Bushnell
    T5: Electronic Testing for SOC Designers. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:20- [Conf]
  3. Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
    Multiple Faults: Modeling, Simulation and Test. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:592-597 [Conf]
  4. Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal
    A testability metric for path delay faults and its application. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:593-598 [Conf]
  5. Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin
    Redundancy Identification Using Transitive Closure. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:4-9 [Conf]
  6. Vishwani D. Agrawal, Kwang-Ting Cheng
    Testing in the Fourth Dimension. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:2-0 [Conf]
  7. Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, P. Pal Chaudhuri
    Panel: New Research Problems in the Emerging Test Technology. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:189-0 [Conf]
  8. Vishwani D. Agrawal, Alok S. Doshi
    Concurrent Test Generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:294-299 [Conf]
  9. Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu
    Collaboration between Industry and Academia in Test Research. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:17-0 [Conf]
  10. Soumitra Bose, Vishwani D. Agrawal
    Sequential logic path delay test generation by symbolic analysis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:353-0 [Conf]
  11. Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell
    False-Path Removal Using Delay Fault Simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:82-87 [Conf]
  12. Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal
    Compaction-based test generation using state and fault information. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:159-164 [Conf]
  13. Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell
    Functional test generation for path delay faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:339-345 [Conf]
  14. Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo
    Sequential Circuit Test Generation on a Distributed System. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:107-111 [Conf]
  15. Vishwani D. Agrawal, Kwang-Ting Cheng
    Test Function Specification in Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:235-240 [Conf]
  16. Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal
    Contest: A Concurrent Test Generator for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:84-89 [Conf]
  17. Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal
    Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:159-164 [Conf]
  18. Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal
    Finite State Machine Synthesis with Fault Tolerant Test Function. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:562-567 [Conf]
  19. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Delay Fault Models and Test Generation for Random Logic Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:165-172 [Conf]
  20. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Design for Testability for Path Delay faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:453-457 [Conf]
  21. Srimat T. Chakradhar, Vishwani D. Agrawal
    A Transitive Closure Based Algorithm for Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:353-358 [Conf]
  22. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell
    Automatic Test Generation Using Quadratic 0-1 Programming. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:654-659 [Conf]
  23. Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal
    An Exact Algorithm for Selecting Partial Scan Flip-Flops. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:81-86 [Conf]
  24. Kwang-Ting Cheng, Vishwani D. Agrawal
    An Entropy Measure for the Complexity of Multi-Output Boolean Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:302-305 [Conf]
  25. Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
    An Efficient Path Delay Fault Coverage Estimator. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:516-521 [Conf]
  26. Prathima Agrawal, Vishwani D. Agrawal, Nripendra N. Biswas
    Multiple output minimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:674-680 [Conf]
  27. Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal
    Efficient spectral techniques for sequential ATPG. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:204-208 [Conf]
  28. Raja K. K. R. Sandireddy, Vishwani D. Agrawal
    Diagnostic and Detection Fault Collapsing for Multiple Output Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1014-1019 [Conf]
  29. José T. de Sousa, Vishwani D. Agrawal
    Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:640-644 [Conf]
  30. Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell
    A New Transitive Closure Algorithm with Application to Redundancy Identification. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:496-500 [Conf]
  31. Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal
    Finite State Machine Testing Based on Growth and Dissappearance Faults. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:238-245 [Conf]
  32. Vishwani D. Agrawal, Sharad C. Seth
    Mutually Disjoint Signals and Probability Calculation in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:307-312 [Conf]
  33. Fei Hu, Vishwani D. Agrawal
    Dual-transition glitch filtering in probabilistic waveform power estimation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:357-360 [Conf]
  34. Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal
    Improving Circuit Testability by Clock Control. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:288-293 [Conf]
  35. Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
    A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:300-0 [Conf]
  36. Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo
    Test Pattern Generation for Sequential Circuits on a Network of Workstations. [Citation Graph (0, 0)][DBLP]
    HPDC, 1993, pp:114-120 [Conf]
  37. Vishwani D. Agrawal, Srimat T. Chakradhar
    Logic Simulation and Parallel Processing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:496-499 [Conf]
  38. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    SIGMA: a simulator for segment delay faults. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:502-508 [Conf]
  39. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    Fast identification of untestable delay faults using implications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:642-647 [Conf]
  40. Fei Hu, Vishwani D. Agrawal
    Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:366-372 [Conf]
  41. Vishwani D. Agrawal
    Design and Test-The Two Sides of a Coin. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:12- [Conf]
  42. Joan Villoldo, Prathima Agrawal, Vishwani D. Agrawal
    Stafan Algorithms for MOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:56-59 [Conf]
  43. Fei Hu, Vishwani D. Agrawal
    Input-specific dynamic power optimization for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:232-237 [Conf]
  44. Vishwani D. Agrawal, Tapan J. Chakraborty
    High-Performance Circuit Testing with Slow-Speed Testers. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:302-310 [Conf]
  45. Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani
    Synthesis of Self-Testing Finite State Machines from High-Level Specifications. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:757-766 [Conf]
  46. Vishwani D. Agrawal, M. Ray Mercer
    Testability Measures : What Do They Tell Us ? [Citation Graph (0, 0)][DBLP]
    ITC, 1982, pp:391-399 [Conf]
  47. Vishwani D. Agrawal, M. Ray Mercer
    Deterministic Versus Random Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:718- [Conf]
  48. Vishwani D. Agrawal
    Will Testability Analysis Replace Fault Simulation ? [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:718-718 [Conf]
  49. Vishwani D. Agrawal
    STAFAN Takes a Middle Course. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:796- [Conf]
  50. Vishwani D. Agrawal
    Panel: Increasing test coverage in a VLSI desgin course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1131- [Conf]
  51. Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, R. Tutundjian
    Fault Simulation in a Pipelined Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:727-734 [Conf]
  52. Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre
    Fault Collapsing via Functional Dominance. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:274-280 [Conf]
  53. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
    Generation of Compact Delay Tests by Multiple-Path Activation. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:714-723 [Conf]
  54. Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski
    Algorithms for Switch Level Delay Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:982-991 [Conf]
  55. Tapan J. Chakraborty, Vishwani D. Agrawal
    Effective Path Selection for Delay Fault Testing of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:998-1003 [Conf]
  56. Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal
    Estimating the Quality of Manufactured Digital Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:210-217 [Conf]
  57. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:139-148 [Conf]
  58. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:276-285 [Conf]
  59. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
    A Synthesis Approach to Design for Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:754-763 [Conf]
  60. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
    Combinational test generation for various classes of acyclic sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1078-1087 [Conf]
  61. M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman
    Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. [Citation Graph (0, 0)][DBLP]
    ITC, 1981, pp:561-565 [Conf]
  62. Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu
    A non-enumerative path delay fault simulator for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:934-943 [Conf]
  63. A. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre
    A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:391-397 [Conf]
  64. Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal
    Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:375-383 [Conf]
  65. Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul
    Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:940-949 [Conf]
  66. Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal
    On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:617-626 [Conf]
  67. Yuanlin Lu, Vishwani D. Agrawal
    Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:217-226 [Conf]
  68. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Design of Variable Input Delay Gates for Low Dynamic Power Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:436-445 [Conf]
  69. Vishwani D. Agrawal, Srimat T. Chakradhar
    Performance estimation in a massively parallel system. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:306-313 [Conf]
  70. Vishwani D. Agrawal
    Choice of Tests for Logic Verification and Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:306-311 [Conf]
  71. Vishwani D. Agrawal
    Science, Technology, and the Indian Society. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:6-9 [Conf]
  72. Vishwani D. Agrawal
    Low-Power Design by Hazard Filtering. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:193-197 [Conf]
  73. Vishwani D. Agrawal, Michael L. Bushnell
    Electronic Testing for SOC Designers (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:20- [Conf]
  74. Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja
    Exclusive Test and its Applications to Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:143-148 [Conf]
  75. Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss
    Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:434-439 [Conf]
  76. Vishwani D. Agrawal, David Lee
    Characteristic polynomial method for verification and test of combinational circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:341-342 [Conf]
  77. Tapan J. Chakraborty, Vishwani D. Agrawal
    Robust testing for stuck-at faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:42-46 [Conf]
  78. Tapan J. Chakraborty, Vishwani D. Agrawal
    Design for high-speed testability of stuck-at faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:53-56 [Conf]
  79. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
    A Path Delay Fault Simulator for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:269-274 [Conf]
  80. Pramit Chavda, James Jacob, Vishwani D. Agrawal
    Optimizing Logic Design Using Boolean Transforms. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:218-221 [Conf]
  81. Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
    Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:723-729 [Conf]
  82. Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
    Power Constraint Scheduling of Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:271-274 [Conf]
  83. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    Parallel concurrent path-delay fault simulation using single-input change patterns. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:426-431 [Conf]
  84. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
    Statistical methods for delay fault coverage analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:166-170 [Conf]
  85. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    Improving accuracy in path delay fault coverage estimation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:422-425 [Conf]
  86. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    A Test Generator for Segment Delay Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:484-491 [Conf]
  87. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
    A Test Function Architecture for Interconnected Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:113-116 [Conf]
  88. James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal
    Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:514-515 [Conf]
  89. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
    Multiple Faults: Modeling, Simulation and Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:592-597 [Conf]
  90. Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal
    Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:143-148 [Conf]
  91. Ananta K. Majhi, Vishwani D. Agrawal
    Mixed-Signal Test. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:285-288 [Conf]
  92. Ananta K. Majhi, Vishwani D. Agrawal
    Tutorial: Delay Fault Models and Coverage. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:364-369 [Conf]
  93. Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal
    An efficient automatic test generation system for path delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:161-165 [Conf]
  94. Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal
    On test coverage of path delay faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:418-421 [Conf]
  95. Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal
    Path Delay Testing: Variable-Clock Versus Rated-Clock. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:470-475 [Conf]
  96. Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
    A Complete Characterization of Path Delay Faults through Stuck-at Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:492-497 [Conf]
  97. Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell
    A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:149-154 [Conf]
  98. Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas
    Statistical path delay fault coverage estimation for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:290-295 [Conf]
  99. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:527-532 [Conf]
  100. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    A Tuturial on the Emerging Nanotechnology Devices. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:343-360 [Conf]
  101. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:1035-1040 [Conf]
  102. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Variable Input Delay CMOS Logic for Low Power Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:598-605 [Conf]
  103. Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
    New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:353-360 [Conf]
  104. James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal
    An asynchronous algorithm for sequential circuit test generation on a network of workstations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:36-41 [Conf]
  105. Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal
    Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:88-94 [Conf]
  106. Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal
    Functional test generation for non-scan sequential circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:47-52 [Conf]
  107. Yuanlin Lu, Vishwani D. Agrawal
    Statistical Leakage and Timing Optimization for Submicron Process Variation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:439-444 [Conf]
  108. P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal
    An Improved Deductive Fault Simulator. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:307-310 [Conf]
  109. Kalyana R. Kantipudi, Vishwani D. Agrawal
    A Reduced Complexity Algorithm for Minimizing N-Detect Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:492-497 [Conf]
  110. Nitin Yogi, Vishwani D. Agrawal
    Spectral RTL Test Generation for Microprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:473-478 [Conf]
  111. Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian
    Power Dissipation During Testing: Should We Worry About it? [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:456-457 [Conf]
  112. Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
    Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:88-93 [Conf]
  113. Tapan J. Chakraborty, Vishwani D. Agrawal
    Simulation of at-speed tests for stuck-at faults. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:216-220 [Conf]
  114. Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal
    Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:163-168 [Conf]
  115. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    Segment delay faults: a new fault model. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:32-41 [Conf]
  116. Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell
    On Delay-Untestable Paths and Stuck-Fault Redundancy. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:194-199 [Conf]
  117. Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul
    Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:182-188 [Conf]
  118. Soumitra Bose, Vishwani D. Agrawal
    Delay Test Quality Evaluation Using Bounded Gate Delays. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:23-28 [Conf]
  119. Vishwani D. Agrawal
    1985 to 1987: My years with D&T. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:173-174 [Journal]
  120. Vishwani D. Agrawal
    1995 Asian Test Symposium carves a niche. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:3-0 [Journal]
  121. Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth
    Generating Tests for Delay Faults in Nonscan Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:1, pp:20-28 [Journal]
  122. Vishwani D. Agrawal, Hatsuyoshi Kato
    Fault Sampling Revisited. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:4, pp:32-35 [Journal]
  123. Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja
    A Tutorial on Built-in Self-Test. I. Principles. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:1, pp:73-82 [Journal]
  124. Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja
    A Tutorial on Built-In Self-Test, Part 2: Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:2, pp:69-77 [Journal]
  125. Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong
    Neural Net and Boolean Satisfiability Models of Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1990, v:7, n:5, pp:54-57 [Journal]
  126. Vishwani D. Agrawal
    Design of mixed-signal systems for testability. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:141-150 [Journal]
  127. Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell
    A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2004, v:19, n:6, pp:955-964 [Journal]
  128. Vishwani D. Agrawal
    An Information Theoretic Approach to Digital Fault Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:8, pp:582-587 [Journal]
  129. Vishwani D. Agrawal
    When to Use Random Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:11, pp:1054-1055 [Journal]
  130. Vishwani D. Agrawal
    Comments on ``An Approach to Highly Integrated Computer-Maintained Cellular Arrays''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:9, pp:691-693 [Journal]
  131. Vishwani D. Agrawal
    Author's Reply. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:8, pp:581- [Journal]
  132. Prathima Agrawal, Vishwani D. Agrawal
    On Monte Carlo Testing of Logic Tree Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:6, pp:664-667 [Journal]
  133. Prathima Agrawal, Vishwani D. Agrawal
    Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:7, pp:691-695 [Journal]
  134. Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal
    Test Generation for Path Delay Faults Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:434-447 [Journal]
  135. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
    Deriving Logic Systems for Path Delay Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:8, pp:829-846 [Journal]
  136. Kwang-Ting Cheng, Vishwani D. Agrawal
    A Partial Scan Method for Sequential Circuits with Feedback. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:544-549 [Journal]
  137. Kwang-Ting Cheng, Vishwani D. Agrawal
    Initializability Consideration in Sequential Machine Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:3, pp:374-379 [Journal]
  138. Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh
    A Simulation-Based Method for Generating Tests for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:12, pp:1456-1463 [Journal]
  139. Sunil K. Jain, Vishwani D. Agrawal
    Modeling and Test Generation Algorithms for MOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:5, pp:426-433 [Journal]
  140. Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat
    A Statistical Theory of Digital Circuit Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:582-586 [Journal]
  141. Vishwani D. Agrawal, Srimat T. Chakradhar
    Combinational ATPG theorems for identifying untestable faults in sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1155-1160 [Journal]
  142. Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal
    A directed search method for test generation using a concurrent simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:131-138 [Journal]
  143. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    On variable clock methods for path delay testing of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1237-1249 [Journal]
  144. Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler
    A transitive closure algorithm for test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1015-1028 [Journal]
  145. Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal
    Toward massively parallel automatic test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:981-994 [Journal]
  146. Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal
    Energy models for delay testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:728-739 [Journal]
  147. Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal
    Redundancy removal and test generation for circuits with non-Boolean primitives. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1370-1377 [Journal]
  148. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    The path-status graph with application to delay fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:324-332 [Journal]
  149. Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal
    A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:873-876 [Journal]
  150. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
    Fault coverage estimation by test vector sampling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:590-596 [Journal]
  151. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel
    Improving a nonenumerative method to estimate path delay fault coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:759-762 [Journal]
  152. Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
    Combinational automatic test pattern generation for acyclic sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:948-956 [Journal]
  153. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
    Test function embedding algorithms with application to interconnected finite state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1115-1127 [Journal]
  154. Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal
    A partition and resynthesis approach to testable design of large circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:10, pp:1268-1276 [Journal]
  155. Sharad C. Seth, Vishwani D. Agrawal
    Characterizing the LSI Yield Equation from Wafer Test Data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:2, pp:123-126 [Journal]
  156. Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal
    Functional test generation for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:7, pp:831-843 [Journal]
  157. Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul
    A test evaluation technique for VLSI circuits using register-transfer level fault modeling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1104-1113 [Journal]
  158. Vishwani D. Agrawal, Srimat T. Chakradhar
    Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:6, pp:739-746 [Journal]
  159. Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal
    Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1245-1255 [Journal]
  160. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
    Path delay fault simulation of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:453-461 [Journal]
  161. D. Das, Sharad C. Seth, Vishwani D. Agrawal
    Accurate computation of field reject ratio based on fault latency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:537-545 [Journal]
  162. Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
    Scheduling tests for VLSI systems under power constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:175-185 [Journal]
  163. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Improving path delay testability of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:736-741 [Journal]
  164. Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell
    Path delay fault simulation of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:223-228 [Journal]
  165. Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
    Transistor Sizing of Logic Gates to Maximize Input Delay Variability. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:121-128 [Journal]
  166. Yuanlin Lu, Vishwani D. Agrawal
    CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:378-387 [Journal]
  167. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:5, pp:459- [Journal]
  168. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:199- [Journal]
  169. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:111- [Journal]
  170. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:5- [Journal]
  171. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:6, pp:567- [Journal]
  172. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:2, pp:111- [Journal]
  173. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:5- [Journal]
  174. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:307- [Journal]
  175. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:111- [Journal]
  176. Vishwani D. Agrawal
    Editorial. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:1, pp:5- [Journal]

  177. Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. [Citation Graph (, )][DBLP]


  178. An adaptive distributed algorithm for sequential circuit test generation. [Citation Graph (, )][DBLP]


  179. An architecture for synthesis of testable finite state machines. [Citation Graph (, )][DBLP]


  180. Polynomial coefficient based DC testing of non-linear analog circuits. [Citation Graph (, )][DBLP]


  181. A tutorial on test power. [Citation Graph (, )][DBLP]


  182. Soft error rate determination for nanoscale sequential logic. [Citation Graph (, )][DBLP]


  183. Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. [Citation Graph (, )][DBLP]


  184. Single Event Upset: An Embedded Tutorial. [Citation Graph (, )][DBLP]


  185. Soft Error Rates with Inertial and Logical Masking. [Citation Graph (, )][DBLP]


  186. Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. [Citation Graph (, )][DBLP]


  187. Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. [Citation Graph (, )][DBLP]


  188. On Minimization of Peak Power for Scan Circuit during Test. [Citation Graph (, )][DBLP]


  189. A diagnostic test generation system and a coverage metric. [Citation Graph (, )][DBLP]


  190. A Two Phase Approach for Minimal Diagnostic Test Set Generation. [Citation Graph (, )][DBLP]


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