The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Laxmi N. Bhuyan: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Laxmi N. Bhuyan, Qing Yang, Dharma P. Agrawal
    Performance of Multiprocessor Interconnection Networks. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:2, pp:25-37 [Journal]
  2. Qing Yang, Laxmi N. Bhuyan, Bao-Chyn Liu
    Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:8, pp:1143-1153 [Journal]
  3. Laxmi N. Bhuyan
    Introduction to session R2 (session overiew): advanced computer architectures. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer Science, 1985, pp:98-99 [Conf]
  4. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan
    Power efficient encoding techniques for off-chip data buses. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:267-275 [Conf]
  5. Zhiyong Xu, Laxmi N. Bhuyan
    Effective Load Balancing in P2P Systems. [Citation Graph (0, 0)][DBLP]
    CCGRID, 2006, pp:81-88 [Conf]
  6. Haiyong Xie, Li Zhao, Laxmi N. Bhuyan
    Architectural analysis and instruction-set optimization for design of network protocol processors. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:225-230 [Conf]
  7. Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan
    Low power network processor design using clock gating. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:712-715 [Conf]
  8. Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
    Utilizing Formal Assertions for System Design of Network Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:126-133 [Conf]
  9. José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan
    A wave-pipelined router architecture using ternary associative memory. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:67-70 [Conf]
  10. Jia Yu, Jun Yang, Shaojie Chen, Yan Luo, Laxmi N. Bhuyan
    Enhancing Network Processor Simulation Speed with Statistical Input Sampling. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2005, pp:68-83 [Conf]
  11. W. Feng, Pavan Balaji, C. Baron, Laxmi N. Bhuyan, Dhabaleswar K. Panda
    Performance Characterization of a 10-Gigabit Ethernet TOE. [Citation Graph (0, 0)][DBLP]
    Hot Interconnects, 2005, pp:58-63 [Conf]
  12. Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravishankar R. Iyer
    Design and Implementation of a Content-Aware Switch Using a Network Processor. [Citation Graph (0, 0)][DBLP]
    Hot Interconnects, 2005, pp:79-85 [Conf]
  13. Ravi R. Iyer, Laxmi N. Bhuyan
    Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:152-160 [Conf]
  14. Marius Pirvu, Laxmi N. Bhuyan, Nan Ni
    The Impact of Link Arbitration on Switch Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:228-235 [Conf]
  15. Jianxun Jason Ding, Laxmi N. Bhuyan
    valuation of multi-queue buffered multistage interconnection networks under uniform and nonuniform traffic patterns. [Citation Graph (0, 0)][DBLP]
    ICCCN, 1995, pp:576- [Conf]
  16. Murali Kadiyala, Laxmi N. Bhuyan
    A dynamic cache sub-block design to reduce false sharing. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:313-0 [Conf]
  17. Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra
    Hierarchical Simulation of a Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:585-588 [Conf]
  18. Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan, Donald Newell
    Hardware Support for Bulk Data Movement in Server Platforms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:53-60 [Conf]
  19. Laxmi N. Bhuyan, Dharma P. Agrawal
    VLSI Performance of Multistage Interconnection Network Using 4*4 Switches. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1982, pp:606-613 [Conf]
  20. Zhong Xu, Rong Huang, Laxmi N. Bhuyan
    Load Balancing of DNS-Based Distributed Web Server Systems with Page Caching. [Citation Graph (0, 0)][DBLP]
    ICPADS, 2004, pp:587-594 [Conf]
  21. Laxmi N. Bhuyan
    Effect of Arbitration Policies on the Performance of Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:4-7 [Conf]
  22. Laxmi N. Bhuyan, Chita R. Das
    Dependability Evaluation of Multicomputer Networks. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:576-583 [Conf]
  23. Laxmi N. Bhuyan, Hong Jiang, Dipak Ghosal
    From Interconnection Network To Task Level Analysis. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1989, pp:73-77 [Conf]
  24. Laxmi N. Bhuyan, C. W. Lee
    An Interference Analysis of Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ICPP, 1983, pp:2-9 [Conf]
  25. Laxmi N. Bhuyan, Bao-Chyn Liu, Irshad Ahmed
    Analysis of MIN Based Multiprocessors with Private Cache Memories. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1989, pp:51-58 [Conf]
  26. Laxmi N. Bhuyan, Ashwini K. Nanda, Tahsin Askar
    Performance and Reliability of the Multistage Bus Network. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:26-33 [Conf]
  27. Laxmi N. Bhuyan, Sumon Shahed, Yeimkuan Chang
    Partitioning an Arbitrary Multicomputer Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1995, pp:215-219 [Conf]
  28. Yeimkuan Chang, Laxmi N. Bhuyan
    Extending Multistage Interconnection Networks for Multitasking. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:151-158 [Conf]
  29. Yeimkuan Chang, Laxmi N. Bhuyan
    Fault Tolerant Subcube Allocation in Hypercubes. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:132-136 [Conf]
  30. Yeimkuan Chang, Laxmi N. Bhuyan
    An Efficient Hybrid Cache Coherence Protocol for Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, Vol. 1, 1996, pp:172-179 [Conf]
  31. Yeimkuan Chang, Laxmi N. Bhuyan, Akhilesh Kumar
    A Distributed Cache Coherence Protocol for Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1994, pp:150-157 [Conf]
  32. Chita R. Das, Laxmi N. Bhuyan
    Reliability Simulation of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ICPP, 1985, pp:591-598 [Conf]
  33. Chita R. Das, Laxmi N. Bhuyan
    Computation Availability of Multiple-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1985, pp:807-813 [Conf]
  34. Jianxun Ding, Laxmi N. Bhuyan
    Performance Evaluation of Multistage Interconnection Networks with Finite Buffers. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:592-599 [Conf]
  35. Jianxun Ding, Laxmi N. Bhuyan
    An Adaptive Submesh Allocation Strategy For Two-Dimensional Mesh Connected Systems. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:193-200 [Conf]
  36. Chao Feng, Laxmi N. Bhuyan, Fabrizio Lombardi
    An Adaptive System-Level Diagnosis Approach for Mesh Connected Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:153-157 [Conf]
  37. Dipak Ghosal, Laxmi N. Bhuyan
    Performance Analysis of the MIT Tagged Token Dataflow Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:680-683 [Conf]
  38. Hong Jiang, Laxmi N. Bhuyan
    Performance Analysis of Layered Task Graphs. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1991, pp:275-279 [Conf]
  39. Hong Jiang, Laxmi N. Bhuyan, Dipak Ghosal
    Approximate Analysis of Multiprocessing Task Graphs. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:228-235 [Conf]
  40. Akhilesh Kumar, Laxmi N. Bhuyan
    Parallel FFT Algorithms for Cache Based Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:23-27 [Conf]
  41. Tong Liu, Wei-Kang Huang, Fabrizio Lombardi, Laxmi N. Bhuyan
    A Submesh Allocation Scheme for Mesh-Connected Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1995, pp:159-163 [Conf]
  42. Ashwini K. Nanda, Laxmi N. Bhuyan
    A Formal Specification and Verification Technique for Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:22-26 [Conf]
  43. Qing Yang, Laxmi N. Bhuyan
    Design and Analysis of a Decentralized Multiple-Bus Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:889-892 [Conf]
  44. Qing Yang, Laxmi N. Bhuyan
    A Queueing Network Model for a Cache Coherence Protocol on Multiple-bus Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:130-137 [Conf]
  45. Ravi R. Iyer, Nancy M. Amato, Lawrence Rauchwerger, Laxmi N. Bhuyan
    Comparing the memory system performance of the HP V-class and SGI Origin 2000 multiprocessors using microbenchmarks and scientific applications. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:339-347 [Conf]
  46. Akhilesh Kumar, Laxmi N. Bhuyan
    Evaluating Virtual Channels for Cache-Coherent Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1996, pp:253-260 [Conf]
  47. Marius Pirvu, Laxmi N. Bhuyan
    Hardware spatial forwarding for widely shared data. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:264-273 [Conf]
  48. Jiani Guo, Jingnan Yao, Laxmi N. Bhuyan
    An efficient packet scheduling algorithm in network processors. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2005, pp:807-818 [Conf]
  49. Nan Ni, Laxmi N. Bhuyan
    Fair Scheduling and Buffer Management in Internet Routers. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2002, pp:- [Conf]
  50. Laxmi N. Bhuyan, Hu-Jun Wang, Ravi R. Iyer, Akhilesh Kumar
    Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:466-474 [Conf]
  51. Yeimkuan Chang, Laxmi N. Bhuyan
    Parallel Algorithms for Hypercube Allocation. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:105-112 [Conf]
  52. S. Chingchit, Mohan Kumar, Laxmi N. Bhuyan
    A Flexible Clustering and Scheduling Scheme for Efficient Parallel Computation. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:500-505 [Conf]
  53. Jiani Guo, Laxmi N. Bhuyan, Raj Kumar, Sujoy Basu
    QoS Aware Job Scheduling in a Cluster-Based Web Server for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  54. Jiani Guo, Fang Chen, Laxmi N. Bhuyan, Raj Kumar
    A Cluster-Based Active Router Architecture Supporting Video/Audio Stream Transcoding Service. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:44- [Conf]
  55. Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
    Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:721-728 [Conf]
  56. Nan Ni, Laxmi N. Bhuyan
    Fair Scheduling for Input Buffered Switches. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:164- [Conf]
  57. Amitabh Mishra, Yeimkuan Chang, Laxmi N. Bhuyan, Fabrizio Lombardi
    Fault-tolerant sorting in SIMD hypercubes. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:312-318 [Conf]
  58. Marius Pirvu, Nan Ni, Laxmi N. Bhuyan
    Exploring the Switch Design Space in a CC-NUMA Multiprocessor Environment. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:703-710 [Conf]
  59. Zhiyong Xu, Yiming Hu, Laxmi N. Bhuyan
    Exploiting Client Cache: A Scalable and Efficient Approach to Build Large Web Cache. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  60. Zhiyong Xu, Rui Min, Laxmi N. Bhuyan, Yiming Hu
    An Efficient and Robust Web Caching System. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  61. Rong Yu, Laxmi N. Bhuyan, Ravi R. Iyer
    Comparing the Memory System Performance of DSS Workloads on the HP V-Class and SGI Origin 2000. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  62. Laxmi N. Bhuyan
    On the Performance of Loosely Coupled Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1984, pp:256-262 [Conf]
  63. Laxmi N. Bhuyan, Dharma P. Agrawal
    A general class of processor interconnection strategies. [Citation Graph (0, 0)][DBLP]
    ISCA, 1982, pp:90-98 [Conf]
  64. Dipak Ghosal, Laxmi N. Bhuyan
    Analytical Modeling and Architectural Modifications of a Dataflow Computer. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:81-89 [Conf]
  65. Dipak Ghosal, Satish K. Tripathi, Laxmi N. Bhuyan, Hong Jiang
    Analysis of Computation-Communication Issues in Dynamic Dataflow Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:325-333 [Conf]
  66. Jiani Guo, Laxmi N. Bhuyan
    Load Sharing in a Transcoding Cluster. [Citation Graph (0, 0)][DBLP]
    IWDC, 2003, pp:330-339 [Conf]
  67. Laxmi N. Bhuyan, Hu-Jun Wang
    Execution-Driven Simulation of IP Router Architectures. [Citation Graph (0, 0)][DBLP]
    NCA, 2001, pp:145-157 [Conf]
  68. Qing Yang, Laxmi N. Bhuyan, R. Pavaskar
    Performance Analysis of Packet-Switched Multiple-Bus Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1987, pp:170-178 [Conf]
  69. Akhilesh Kumar, Phanindra K. Mannava, Laxmi N. Bhuyan
    Efficient and scalable cache coherence schemes for shared memory hypercube multiprocessors. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:498-507 [Conf]
  70. Ashwini K. Nanda, Laxmi N. Bhuyan
    Mapping Applications onto a Cache Coherent Multiprocessor. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:368-377 [Conf]
  71. Dipak Ghosal, Laxmi N. Bhuyan, Uday Choudhury
    Approximate Analysis of Task Graphs for Parallel Processing Systems. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1988, pp:274- [Conf]
  72. Jianxun Ding, Laxmi N. Bhuyan
    Cache Coherent Shared Memory Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SPDP, 1992, pp:515-520 [Conf]
  73. Chao Feng, Laxmi N. Bhuyan, Fabrizio Lombardi
    An Adaptive System-Level Diagnosis Approach for Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:460-469 [Conf]
  74. Qing Yang, George Thangadurai, Laxmi N. Bhuyan
    An adaptive cache coherence scheme for hierarchical shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    SPDP, 1990, pp:318-325 [Conf]
  75. Laxmi N. Bhuyan
    Application Oriented Networking (AON): Adding Intelligence to Next-Generation Internet Routers. [Citation Graph (0, 0)][DBLP]
    WASA, 2006, pp:1-2 [Conf]
  76. Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer
    SpliceNP: a TCP splicer using a network processor. [Citation Graph (0, 0)][DBLP]
    ANCS, 2005, pp:135-143 [Conf]
  77. Nan Ni, Laxmi N. Bhuyan
    Fair Scheduling for Input Buffered Switches. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 2003, v:6, n:2, pp:105-114 [Journal]
  78. Chita R. Das, Jeffrey T. Kreulen, Matthew Thazhuthaveetil, Laxmi N. Bhuyan
    Dependability Modeling for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:10, pp:7-19 [Journal]
  79. Ravi R. Iyer, Jack Perdue, Lawrence Rauchwerger, Nancy M. Amato, Laxmi N. Bhuyan
    An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:4, pp:307-350 [Journal]
  80. Chita R. Das, Laxmi N. Bhuyan
    Dependability evaluation of interconnection networks. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1987, v:43, n:1-2, pp:107-138 [Journal]
  81. Laxmi N. Bhuyan
    Analysis of Interconnection Networks with Different Arbiter Designs. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1987, v:4, n:4, pp:384-403 [Journal]
  82. Hong Jiang, Laxmi N. Bhuyan, Jogesh K. Muppala
    MVAMIN: Mean Value Analysis Algorithms for Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1991, v:12, n:3, pp:189-201 [Journal]
  83. Ashwini K. Nanda, Laxmi N. Bhuyan
    Efficient Mapping of Applications on Cache Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:19, n:3, pp:179-191 [Journal]
  84. Qing Yang, Laxmi N. Bhuyan
    Performance of Multiple-Bus Interconnections for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1990, v:8, n:3, pp:267-273 [Journal]
  85. Xiao Zhang, Laxmi N. Bhuyan, Wu-chun Feng
    Anatomy of UDP and M-VIA for cluster communication. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2005, v:65, n:10, pp:1290-1298 [Journal]
  86. Ravishankar R. Iyer, Hu-Jun Wang, Laxmi N. Bhuyan
    Design and analysis of static memory management policies for CC-NUMA multiprocessors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:1-3, pp:59-80 [Journal]
  87. Yan Luo, Jun Yang, Laxmi N. Bhuyan, Li Zhao
    NePSim: A Network Processor Simulator with a Power Evaluation Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:5, pp:34-44 [Journal]
  88. Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer
    A Network Processor-Based, Content-Aware Switch. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:3, pp:72-84 [Journal]
  89. Vamsee Lakamsani, Laxmi N. Bhuyan, D. Scott Linthicum
    Mapping Molecular Dynamics Computations on to Hypercubes. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1995, v:21, n:6, pp:993-1013 [Journal]
  90. Laxmi N. Bhuyan
    An Analysis of Processor-Memory Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:3, pp:279-283 [Journal]
  91. Laxmi N. Bhuyan, Dharma P. Agrawal
    On the Generalized Binary System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:4, pp:335-338 [Journal]
  92. Laxmi N. Bhuyan, Dharma P. Agrawal
    Design and Performance of Generalized Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:12, pp:1081-1090 [Journal]
  93. Laxmi N. Bhuyan, Dharma P. Agrawal
    Generalized Hypercube and Hyperbus Structures for a Computer Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:4, pp:323-333 [Journal]
  94. Laxmi N. Bhuyan, Dipak Ghosal, Qing Yang
    Approximate Analysis of Single and Multiple Ring Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:7, pp:1027-1040 [Journal]
  95. Laxmi N. Bhuyan, Hu-Jun Wang
    Switch MSHR: A Technique to Reduce Remote Read Memory Access Time in CC-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:5, pp:617-632 [Journal]
  96. Yeimkuan Chang, Laxmi N. Bhuyan
    A Combinatorial Analysis of Subcube Reliability in Hybercubes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:7, pp:952-956 [Journal]
  97. Yeimkuan Chang, Laxmi N. Bhuyan
    Subcube Fault Tolerance in Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:9, pp:1108-1120 [Journal]
  98. Yeimkuan Chang, Laxmi N. Bhuyan
    An Efficient Tree Cache Coherence Protocol for Distributed Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:3, pp:352-360 [Journal]
  99. Chita R. Das, Laxmi N. Bhuyan
    Bandwidth Availability of Multiple-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:10, pp:918-926 [Journal]
  100. Jianxun Ding, Laxmi N. Bhuyan
    Finite Buffer Analysis of Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:2, pp:243-247 [Journal]
  101. Chao Feng, Laxmi N. Bhuyan, Fabrizio Lombardi
    Adaptive System-Level Diagnosis for Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:10, pp:1157-1170 [Journal]
  102. Dipak Ghosal, Laxmi N. Bhuyan
    Performance Evaluation of a Dataflow Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:5, pp:615-627 [Journal]
  103. Ravi R. Iyer, Laxmi N. Bhuyan
    Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:8, pp:779-797 [Journal]
  104. Nan Ni, Laxmi N. Bhuyan
    Fair Scheduling in Internet Routers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:6, pp:686-701 [Journal]
  105. Ashwini K. Nanda, Laxmi N. Bhuyan
    Design and Analysis of Cache Coherent Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:4, pp:458-470 [Journal]
  106. V. C. Ravikumar, Rabi N. Mahapatra, Laxmi N. Bhuyan
    EaseCAM: An Energy and Storage Efficient TCAM-Based Router Architecture for IP Lookup. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:5, pp:521-533 [Journal]
  107. Qing Yang, Laxmi N. Bhuyan
    Analysis of Packet-Switched Multiple-Bus Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:3, pp:352-356 [Journal]
  108. Li Zhao, Laxmi N. Bhuyan, Ravi R. Iyer, Srihari Makineni, Donald Newell
    Hardware Support for Accelerating Data Movement in Server Platform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:6, pp:740-753 [Journal]
  109. Zhiyong Xu, Laxmi N. Bhuyan, Yiming Hu
    Tulip: A New Hash Based Cooperative Web Caching Architecture. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:35, n:3, pp:301-320 [Journal]
  110. Laxmi N. Bhuyan
    Editorial: A Message from the New Editor-in-Chief. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:1, pp:2- [Journal]
  111. Laxmi N. Bhuyan
    Editor's Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:5, pp:401-402 [Journal]
  112. Laxmi N. Bhuyan, Ravi R. Iyer, Tahsin Askar, Ashwini K. Nanda, Mohan Kumar
    Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:1, pp:82-95 [Journal]
  113. Laxmi N. Bhuyan, Ravi R. Iyer, Hu-Jun Wang, Akhilesh Kumar
    Impact of CC-NUMA Memory Management Policies on the Application Performance of Multistage Switching Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:3, pp:230-246 [Journal]
  114. Chita R. Das, Prasant Mohapatra, Lei Tien, Laxmi N. Bhuyan
    An Availability Model for MIN-Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:10, pp:1118-1129 [Journal]
  115. Jiani Guo, Laxmi N. Bhuyan
    Load Balancing in a Cluster-Based Web Server for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:11, pp:1321-1334 [Journal]
  116. Qing Yang, George Thangadurai, Laxmi N. Bhuyan
    Design of an Adaptive Cache Coherence Protocol for Large Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:3, pp:281-293 [Journal]
  117. Laxmi N. Bhuyan
    Editor's Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:1, pp:1-2 [Journal]
  118. Laxmi N. Bhuyan, Dharma P. Agrawal
    Performance Analysis of FFT Algorithms on Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1983, v:9, n:4, pp:512-521 [Journal]
  119. Jia Yu, Jingnan Yao, Laxmi N. Bhuyan, Jun Yang
    Program Mapping onto Network Processors by Recursive Bipartitioning and Refining. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:805-810 [Conf]
  120. Xiao Zhang, Satya Ranjan Mohanty, Laxmi N. Bhuyan
    Adaptive Max-Min Fair Scheduling in Buffered Crossbar Switches Without Speedup. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2007, pp:454-462 [Conf]
  121. Satya Ranjan Mohanty, Laxmi N. Bhuyan
    Lexicographic Fairness in WDM Optical Cross-Connects. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2007, pp:197-205 [Conf]
  122. Z. Xu, X. He, Laxmi N. Bhuyan
    Efficient file sharing strategy in DHT based P2P systems. [Citation Graph (0, 0)][DBLP]
    IPCCC, 2005, pp:151-158 [Conf]
  123. Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan
    Conserving network processor power consumption by exploiting traffic variability. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:1, pp:- [Journal]
  124. Laxmi N. Bhuyan
    Editor's Note. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:9, pp:1185-1187 [Journal]

  125. Applications of SIMD computers in signal processing. [Citation Graph (, )][DBLP]


  126. A new IP lookup cache for high performance IP routers. [Citation Graph (, )][DBLP]


  127. LATA: a latency and throughput-aware packet processing system. [Citation Graph (, )][DBLP]


  128. Revisiting the Cache Effect on Multicore Multithreaded Network Processors. [Citation Graph (, )][DBLP]


  129. Intelligent Message Scheduling in Application Oriented Networking Systems. [Citation Graph (, )][DBLP]


  130. A Novel Service-Aware Message Scheduler for Cisco Application Oriented Networking Systems. [Citation Graph (, )][DBLP]


  131. Load balancing with network cooperation. [Citation Graph (, )][DBLP]


  132. Quantum-Adaptive Scheduling for Multi-Core Network Processors. [Citation Graph (, )][DBLP]


  133. A Hash-based Scalable IP lookup using Bloom and Fingerprint Filters. [Citation Graph (, )][DBLP]


  134. Design and performance of a general class of interconnection networks. [Citation Graph (, )][DBLP]


  135. Equalization of Digital Communication Channen Using Hartley-Neural Technique. [Citation Graph (, )][DBLP]


  136. Cyber-Fraud is One Typo Away. [Citation Graph (, )][DBLP]


  137. Budget-Based Self-Optimized Incentive Search in Unstructured P2P Networks. [Citation Graph (, )][DBLP]


  138. Optimizing Throughput and Latency under Given Power Budget for Network Packet Processing. [Citation Graph (, )][DBLP]


  139. A Balanced Consistency Maintenance Protocol for Structured P2P Systems. [Citation Graph (, )][DBLP]


  140. An effective pointer replication algorithm in P2P networks. [Citation Graph (, )][DBLP]


  141. PROD: Relayed file retrieving in overlay networks. [Citation Graph (, )][DBLP]


  142. Anatomy and Performance of SSL Processing. [Citation Graph (, )][DBLP]


  143. Fair Scheduling over multiple servers with flow-dependent server rate. [Citation Graph (, )][DBLP]


  144. Computing Real Time Jobs in P2P Networks. [Citation Graph (, )][DBLP]


  145. The P2P War: Someone Is Monitoring Your Activities! [Citation Graph (, )][DBLP]


  146. Multistage bus network (MBN): an interconnection network for cache coherent multiprocessors. [Citation Graph (, )][DBLP]


  147. POND: The Power of Zone Overlapping in DHT Networks. [Citation Graph (, )][DBLP]


  148. Performance Characterization of a Dual Quad-Core Based Application Oriented Networking System. [Citation Graph (, )][DBLP]


  149. Compiling PCRE to FPGA for accelerating SNORT IDS. [Citation Graph (, )][DBLP]


  150. Flow-slice: a novel load-balancing scheme for multi-path switching systems. [Citation Graph (, )][DBLP]


  151. A scalable multithreaded L7-filter design for multi-core servers. [Citation Graph (, )][DBLP]


  152. Software techniques to improve virtualized I/O performance on multi-core systems. [Citation Graph (, )][DBLP]


  153. Efficient server cooperation mechanism in content delivery network. [Citation Graph (, )][DBLP]


  154. Scalable and Decentralized Content-Aware Dispatching in Web Clusters. [Citation Graph (, )][DBLP]


  155. Performance characterization and cache-aware core scheduling in a virtualized multi-core server under 10GbE. [Citation Graph (, )][DBLP]


  156. Clustered K-Center: Effective Replica Placement in Peer-to-Peer Systems. [Citation Graph (, )][DBLP]


  157. The P2P war: Someone is monitoring your activities. [Citation Graph (, )][DBLP]


  158. Fair link striping with FIFO delivery on heterogeneous channels. [Citation Graph (, )][DBLP]


Search in 0.007secs, Finished in 0.756secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002