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Publications of Author

1. Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou
   Track assignment: a desirable intermediate step between global routing and detailed routing. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2002, pp:59-66 [Conf]
   
2. Rohit Ananthakrishna, Shabbir H. Batterywala
   MoM - A Process Variation Aware Statistical Capacitance Extractor. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:135-140 [Conf]
   
3. Shabbir H. Batterywala, Rohit Ananthakrishna, Yansheng Luo, Alex Gyure
   A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2006, pp:129-134 [Conf]
   
4. Shabbir H. Batterywala, Madhav P. Desai
   Variance Reduction in Monte Carlo Capacitance Extraction. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:85-90 [Conf]
   
5. Shabbir H. Batterywala, H. Narayanan
   Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2001, pp:500-0 [Conf]
   
6. Shabbir H. Batterywala, H. Narayanan
   Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:169-174 [Conf]
   
7. Shabbir H. Batterywala, Narendra V. Shenoy
   A Method to Estimate Slew and Delay in Coupled Digital Circuits. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:411-416 [Conf]
   
8. Shabbir H. Batterywala, Narendra V. Shenoy
   Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:989-994 [Conf]
   
9. Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan
   A New Partitioning Strategy Based on Supermodular Functions. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1997, pp:32-37 [Conf]
   
10. Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
    Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:875-880 [Conf]
    
11. Subramanian Rajagopalan, Shabbir H. Batterywala
    A 3-dimensional FEM Based Resistance Extraction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:565-570 [Conf]
    
12. 
    On Efficient and Robust Constraint Generation for Practical Layout Legalization. [Citation Graph (, )][DBLP]
    
    
13. 
    Cell Swapping Based Migration Methodology for Analog and Custom Layouts. [Citation Graph (, )][DBLP]
    
    
14. 
    Efficient Analog/RF Layout Closure with Compaction Based Legalization. [Citation Graph (, )][DBLP]