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Xuejue Huang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester
    Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:56-61 [Conf]
  2. Yu Cao, Xiao-Dong Yang, Xuejue Huang, Dennis Sylvester
    Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:848-854 [Conf]
  3. Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie
    Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:185-190 [Conf]
  4. Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu
    Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:158-162 [Journal]
  5. Yu Cao, Xiao-Dong Yang, Xuejue Huang, Dennis Sylvester
    Switch-factor based loop RLC modeling for efficient timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1072-1078 [Journal]
  6. Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu
    Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:799-805 [Journal]
  7. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
    Improved a priori interconnect predictions and technology extrapolation in the GTX system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:3-14 [Journal]

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