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Mitrajit Chatterjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
    LOT: logic optimization with testability-new transformations using recursive learning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:318-325 [Conf]
  2. Dhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee
    Buffer assignment for data driven architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:665-668 [Conf]
  3. Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee
    VERILAT: verification using logic augmentation and transformations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:88-95 [Conf]
  4. Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz
    Gate-level synthesis for low-power using new transformations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:297-300 [Conf]
  5. Dhiraj K. Pradhan, Mitrajit Chatterjee
    GLFSR - A New Test Pattern Generator for Built-In Self-Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:481-490 [Conf]
  6. Mitrajit Chatterjee, Dhiraj K. Pradhan
    A novel pattern generator for near-perfect fault-coverage. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:417-425 [Conf]
  7. Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan
    Buffer Assignment Algorithms on Data Driven ASICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:1, pp:16-32 [Journal]
  8. Mitrajit Chatterjee, Dhiraj K. Pradhan
    A BIST Pattern Generator Design for Near-Perfect Fault Coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:12, pp:1543-1558 [Journal]
  9. Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
    LOT: Logic Optimization with Testability. New transformations for logic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:386-399 [Journal]
  10. Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan
    VERILAT: verification using logic augmentation and transformations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1041-1051 [Journal]
  11. Dhiraj K. Pradhan, Mitrajit Chatterjee
    GLFSR-a new test pattern generator for built-in-self-test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:238-247 [Journal]

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