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Yu-Wen Tsay: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-optimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:123-127 [Conf]
  2. Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin
    Integrating logic retiming and register placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:136-139 [Conf]
  3. Yu-Wen Tsay, Wen-Jong Fang, Allen C.-H. Wu, Youn-Long Lin
    Preserving HDL synthesis hierarchy for cell placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:169-174 [Conf]
  4. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-minimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1076-1084 [Journal]
  5. Yu-Wen Tsay, Youn-Long Lin
    A row-based cell placement method that utilizes circuit structural properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:393-397 [Journal]

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