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Ruiming Chen :
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Ruiming Chen , Hai Zhou Timing macro-modeling of IP blocks with crosstalk. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:155-159 [Conf ] Ruiming Chen , Hai Zhou Clock schedule verification under process variations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:619-625 [Conf ] Ruiming Chen , Hai Zhou Efficient algorithms for buffer insertion in general circuits based on network flow. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:322-326 [Conf ] Ruiming Chen , Hai Zhou A Flexible Data Structure for Efficient Buffer Insertion. [Citation Graph (0, 0)][DBLP ] ICCD, 2004, pp:216-221 [Conf ] Ruiming Chen , Hai Zhou Statistical timing verification for transparently latched circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1847-1855 [Journal ] Ruiming Chen , Hai Zhou Fast Min-Cost Buffer Insertion under Process Variations. [Citation Graph (0, 0)][DBLP ] DAC, 2007, pp:338-343 [Conf ] Fast Buffer Insertion for Yield Optimization Under Process Variations. [Citation Graph (, )][DBLP ] Static timing: Back to our roots. [Citation Graph (, )][DBLP ] New Block-Based Statistical Timing Analysis Approaches Without Moment Matching. [Citation Graph (, )][DBLP ] Timing budgeting under arbitrary process variations. [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.002secs