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Peter Bendix: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Yannick L. Le Coz, Dhivya Krishna, Dusan M. Petranovic, William M. Loh, Peter Bendix
A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines. [Citation Graph (0, 0)][DBLP]
ICCAD, 2003, pp:665-671 [Conf] - Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems. [Citation Graph (0, 0)][DBLP]
ICCD, 2001, pp:406-414 [Conf] - Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang
Full chip ESD design rule checking. [Citation Graph (0, 0)][DBLP]
ISCAS (5), 2001, pp:503-506 [Conf] - Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang
ESD design rule checker. [Citation Graph (0, 0)][DBLP]
ISCAS (5), 2001, pp:499-502 [Conf] - Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology. [Citation Graph (0, 0)][DBLP]
ISCAS (4), 2001, pp:746-749 [Conf] - Peter Bendix
Spice Model Quality: Process Development Viewpoint. [Citation Graph (0, 0)][DBLP]
ISQED, 2001, pp:477-481 [Conf] - Yoon Huh, Peter Bendix, Kyungjin Min, Jau-Wen Chen, Ravindra Narayan, Larry D. Johnson, Steven H. Voldman
ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited. [Citation Graph (0, 0)][DBLP]
IWSOC, 2005, pp:47-53 [Conf] - Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix
Prediction of interconnect adjacency distribution: derivation, validation, and applications. [Citation Graph (0, 0)][DBLP]
SLIP, 2004, pp:99-106 [Conf] - Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
Chip-level charged-device modeling and simulation in CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:67-81 [Journal]
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