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Anthony Vannelli :
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Hussein Etawil , Shawki Areibi , Anthony Vannelli Attractor-repeller approach for global placement. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:20-24 [Conf ] Kristofer Vorwerk , Andrew A. Kennings , Anthony Vannelli Engineering details of a stable force-directed placer. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:573-580 [Conf ] Tamás Terlaky , Anthony Vannelli , Hu Zhang On Routing in VLSI Design and Communication Networks. [Citation Graph (0, 0)][DBLP ] ISAAC, 2005, pp:1051-1060 [Conf ] Shawki Areibi , Anthony Vannelli Circuit Partitioning Using a Tabu Search Approach. [Citation Graph (0, 0)][DBLP ] ISCAS, 1993, pp:1643-1646 [Conf ] P. Chin , Anthony Vannelli Interior Point Methods for Placement. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:169-172 [Conf ] L. Song , Mohamed I. Elmasry , Anthony Vannelli Analog neural network building blocks based on current mode subthreshold operation. [Citation Graph (0, 0)][DBLP ] ISCAS, 1993, pp:2462-2465 [Conf ] Laleh Behjat , Anthony Vannelli VLSI concentric partitioning using interior point quadratic programming. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 1999, pp:93-96 [Conf ] Laleh Behjat , Anthony Vannelli Steiner Tree Construction Based on Congestion for the Global Routing Problem. [Citation Graph (0, 0)][DBLP ] IWSOC, 2003, pp:28-31 [Conf ] Dorothy Kucar , Anthony Vannelli InterconnectionModelling Using Distributed RLC Models. [Citation Graph (0, 0)][DBLP ] IWSOC, 2003, pp:32-35 [Conf ] P. L. Takouda , Miguel F. Anjos , Anthony Vannelli Global Lower Bounds for the VLSI Macrocell Floorplanning Problem Using Semidefinite Optimization. [Citation Graph (0, 0)][DBLP ] IWSOC, 2005, pp:275-280 [Conf ] Anthony Vannelli A Parallel Implementation of an Interior Point Method for Linear Programming. [Citation Graph (0, 0)][DBLP ] PPSC, 1991, pp:163-167 [Conf ] Mohamed Saad , Tamás Terlaky , Anthony Vannelli , Hu Zhang Packing Trees in Communication Networks. [Citation Graph (0, 0)][DBLP ] WINE, 2005, pp:688-697 [Conf ] Weiguo Liu , Anthony Vannelli Generating Lower Bounds for the Linear Arrangement Problem. [Citation Graph (0, 0)][DBLP ] Discrete Applied Mathematics, 1995, v:59, n:2, pp:137-151 [Journal ] C.-J. Richard Shi , Anthony Vannelli , Jiri Vlach Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning. [Citation Graph (0, 0)][DBLP ] J. Heuristics, 1997, v:3, n:3, pp:225-243 [Journal ] Miguel F. Anjos , Anthony Vannelli A New Mathematical-Programming Framework for Facility-Layout Design. [Citation Graph (0, 0)][DBLP ] INFORMS Journal on Computing, 2006, v:18, n:1, pp:111-118 [Journal ] Shawki Areibi , Anthony Vannelli Tabu Search: Implementation & Complexity Analysis for Netlist Partitioning. [Citation Graph (0, 0)][DBLP ] I. J. Comput. Appl., 2003, v:10, n:4, pp:211-232 [Journal ] Laleh Behjat , Dorothy Kucar , Anthony Vannelli A Novel Eigenvector Technique for Large Scale Combinatorial Problems in VLSI Layout. [Citation Graph (0, 0)][DBLP ] J. Comb. Optim., 2002, v:6, n:3, pp:271-286 [Journal ] Earl R. Barnes , Anthony Vannelli , James Q. Walker A New Heuristic for Partitioning the Nodes of a Graph. [Citation Graph (0, 0)][DBLP ] SIAM J. Discrete Math., 1988, v:1, n:3, pp:299-305 [Journal ] Scott W. Hadley , Brian L. Mark , Anthony Vannelli An efficient eigenvector approach for finding netlist partitions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:885-892 [Journal ] Anthony Vannelli An adaptation of the interior point method for solving the global routing problem. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:193-203 [Journal ] Jiri Vlach , James A. Barby , Anthony Vannelli , T. Talkhan , C.-J. Richard Shi Group delay as an estimate of delay in logic. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:949-953 [Journal ] Large-scale fixed-outline floorplanning design using convex optimization techniques. [Citation Graph (, )][DBLP ] On the Computational Performance of a Semidefinite Programming Approach to Single Row Layout Problems. [Citation Graph (, )][DBLP ] On routing in VLSI design and communication networks. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.301secs