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Yanbin Jiang:
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- Yanbin Jiang, Sachin S. Sapatnekar
An integrated algorithm for combined placement and libraryless technology mapping. [Citation Graph (0, 0)][DBLP] ICCAD, 1999, pp:102-106 [Conf]
- Juho Kim, Cyrus Bamji, Yanbin Jiang, Sachin S. Sapatnekar
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs. [Citation Graph (0, 0)][DBLP] ISPD, 1997, pp:130-135 [Conf]
- Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim
Interleaving buffer insertion and transistor sizing into a single optimization. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:625-633 [Journal]
- Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji
Technology mapping for high-performance static CMOS and pass transistor logic designs. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:577-589 [Journal]
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