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Kerry S. Lowe: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kerry S. Lowe, P. Glenn Gulak
    Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:216-219 [Conf]
  2. Kerry S. Lowe, P. Glenn Gulak
    A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:419-434 [Journal]

  3. A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits. [Citation Graph (, )][DBLP]


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