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Publications of Author

1. Pradip Mandal, V. Visvanathan
   Macromodeling of the A.C. characteristics of CMOS Op-amps. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1993, pp:334-340 [Conf]
   
2. Gunjan Mandal, Pradip Mandal
   Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2004, pp:1120-1123 [Conf]
   
3. Gunjan Mandal, Pradip Mandal
   Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface. [Citation Graph (0, 0)][DBLP]
   ISCAS (3), 2005, pp:2180-2183 [Conf]
   
4. Debashis Mandal, Pradip Mandal
   High voltage tolerant output buffer design for mixed voltage interfaces. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2005, pp:4277-4280 [Conf]
   
5. Ashis Maity, R. G. Raghavendra, Pradip Mandal
   On-Chip Voltage Regulator with Improved Transient Response. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:522-527 [Conf]
   
6. Pradip Mandal
   A Narrow Pulse- Suppressing Filter For Input Buffer. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:701-704 [Conf]
   
7. Pradip Mandal, V. Visvanathan
   Design of high performance two stage CMOS cascode op-amps with stable biasing. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1996, pp:234-237 [Conf]
   
8. Pradip Mandal, V. Visvanathan
   A Self-Biased High Performance Folded Cascode CMOS Op-Amp. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1997, pp:429-434 [Conf]
   
9. Pradip Mandal, V. Visvanathan
   A New Approach for CMOS Op-Amp Synthesis. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:189-195 [Conf]
   
10. S. S. Prasad, Pradip Mandal
    A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:551-0 [Conf]
    
11. R. G. Raghavendra, Pradip Mandal
    An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power Efficiency. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:331-336 [Conf]
    
12. Pradip Mandal, V. Visvanathan
    CMOS op-amp sizing using a geometric programming formulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:22-38 [Journal]
    
13. 
    An automated design approach for CMOS LDO regulators. [Citation Graph (, )][DBLP]
    
    
14. 
    A single circuit solution for voltage sensors. [Citation Graph (, )][DBLP]
    
    
15. 
    Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination. [Citation Graph (, )][DBLP]
    
    
16. 
    Integrated TIA-Equalizer for High Speed Optical Link. [Citation Graph (, )][DBLP]
    
    
17. 
    A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter. [Citation Graph (, )][DBLP]
    
    
18. 
    Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple. [Citation Graph (, )][DBLP]
    
    
19. 
    An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology. [Citation Graph (, )][DBLP]
    
    
20. 
    On-Chip Inductor-Less DC-DC Boost Converter with Non-overlapped Rotational-Interleaving Scheme. [Citation Graph (, )][DBLP]
    
    
21. 
    Design and Analysis of a VHF OTA-C Cell for Optimum Phase Response. [Citation Graph (, )][DBLP]
    
    
22. 
    Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing. [Citation Graph (, )][DBLP]