Search the dblp DataBase

Publications of Author

1. Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
   Rectangle-packing-based module placement. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:472-479 [Conf]
   
2. Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
   Module placement on BSG-structure and IC layout applications. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1996, pp:484-491 [Conf]
   
3. Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
   The Totally-Perfect Bipartite Graph and Its Construction. [Citation Graph (0, 0)][DBLP]
   ISAAC, 1994, pp:541-549 [Conf]
   
4. Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
   Design of Optimum Totally Perfect Connection-Blocks of FPGA. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:221-224 [Conf]
   
5. Chikaaki Kodama, Kunihiro Fujiyoshi, Teppei Koga
   A novel encoding method into sequence-pair. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2004, pp:329-332 [Conf]
   
6. Kunihiro Fujiyoshi, Hiroshi Murata
   Arbitrary convex and concave rectilinear block packing using sequence-pair. [Citation Graph (0, 0)][DBLP]
   ISPD, 1999, pp:103-110 [Conf]
   
7. Shinichi Kouda, Chikaaki Kodama, Kunihiro Fujiyoshi
   Improved method of cell placement with symmetry constraints for analog IC layout design. [Citation Graph (0, 0)][DBLP]
   ISPD, 2006, pp:192-199 [Conf]
   
8. Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko
   VLSI/PCB placement with obstacles based on sequence-pair. [Citation Graph (0, 0)][DBLP]
   ISPD, 1997, pp:26-31 [Conf]
   
9. Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu
   Design of minimum and uniform bipartites for optimum connection blocks of FPGA. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1377-1383 [Journal]
   
10. Kunihiro Fujiyoshi, Hiroshi Murata
    Arbitrary convex and concave rectilinear block packing usingsequence-pair. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:224-233 [Journal]
    
11. Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
    Module packing based on the BSG-structure and IC layout applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:519-530 [Journal]
    
12. Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko
    VLSI/PCB placement with obstacles based on sequence pair. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:60-68 [Journal]
    
13. Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
    VLSI module placement based on rectangle-packing by the sequence-pair. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1518-1524 [Journal]
    
14. Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara
    DTS: A Tree Based Representation for 3D-Block Packing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1045-1048 [Conf]
    
15. Y. Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, A. Takahashi
    Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
16. Kunihiro Fujiyoshi, Chikaaki Kodama, Akira Ikeda
    A fast algorithm for rectilinear block packing based on selected sequence-pair. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:3, pp:274-284 [Journal]
    
17. 
    Thermal Driven Module Placement Using Sequence-pair. [Citation Graph (, )][DBLP]
    
    
18. 
    An efficient decoding method of sequence-pair. [Citation Graph (, )][DBLP]
    
    
19. 
    An improved method of convex-shaped block packing based on sequence-pair [VLSI layout]. [Citation Graph (, )][DBLP]