Search the dblp DataBase

Publications of Author

1. Ravindranath Naiknaware, Terri S. Fiez
   CMOS analog circuit stack generation with matching constraints. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:371-375 [Conf]
   
2. Ravindranath Naiknaware
   Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment. [Citation Graph (0, 0)][DBLP]
   ICCD, 1993, pp:318-321 [Conf]
   
3. Ravindranath Naiknaware, Terri S. Fiez
   Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 1999, pp:33-36 [Conf]
   
4. Ravindranath Naiknaware, Terri S. Fiez
   Switched-capacitor integrator design optimizing for power and process variations. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 1999, pp:278-281 [Conf]
   
5. Ravindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa
   Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. [Citation Graph (0, 0)][DBLP]
   ITC, 1993, pp:139-148 [Conf]
   
6. Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin
   Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1993, pp:140-143 [Conf]