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Dinesh Pamunuwa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen
    Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:835-842 [Conf]
  2. Jian Liu, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
    A global wire planning scheme for Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:892-895 [Conf]
  3. Dinesh Pamunuwa, Shauki Elassaad
    Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:604-607 [Conf]
  4. Hannu Tenhunen, Dinesh Pamunuwa
    On dynamic delay and repeater insertion. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:97-100 [Conf]
  5. Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
    Optimising bandwidth over deep sub-micron interconnect. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:193-196 [Conf]
  6. Dinesh Pamunuwa, Hannu Tenhunen
    On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:240-245 [Conf]
  7. Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
    Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:277-285 [Conf]
  8. Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
    Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:113-120 [Conf]
  9. Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch
    Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:362-0 [Conf]
  10. Dinesh Pamunuwa, Hannu Tenhunen
    Repeater Insertion To Minimise Delay In Coupled Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:513-517 [Conf]
  11. Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
    Delay-Balanced Smart Repeaters for On-Chip Global Signaling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:308-313 [Conf]
  12. Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen
    A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:1, pp:3-17 [Journal]
  13. Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen
    Modeling delay and noise in arbitrarily coupled RC trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1725-1739 [Journal]
  14. Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
    Maximizing throughput over parallel wire structures in the deep submicrometer regime. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:224-243 [Journal]

  15. Memory Technology for Extended Large-Scale Integration in Future Electronics Applications. [Citation Graph (, )][DBLP]


  16. On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. [Citation Graph (, )][DBLP]


  17. Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. [Citation Graph (, )][DBLP]


  18. Scalability of network-on-chip communication architecture for 3-D meshes. [Citation Graph (, )][DBLP]


  19. Application of Molecular Electronics Devices in Digital Circuit Design. [Citation Graph (, )][DBLP]


  20. Designing Reliable Digital Molecular Electronic Circuits. [Citation Graph (, )][DBLP]


  21. Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. [Citation Graph (, )][DBLP]


  22. Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. [Citation Graph (, )][DBLP]


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