Search the dblp DataBase

Publications of Author

1. Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown
   A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:689-692 [Conf]
   
2. Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
   Power-aware global signaling strategies. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2005, pp:604-607 [Conf]
   
3. Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
   Leakage and leakage sensitivity computation for combinational circuits. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:96-99 [Conf]
   
4. Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif
   Approaches to run-time and standby mode leakage reduction in global buses. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2004, pp:188-193 [Conf]
   
5. Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown
   Efficient techniques for gate leakage estimation. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:100-103 [Conf]
   
6. Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
   Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. [Citation Graph (0, 0)][DBLP]
   ISQED, 2005, pp:88-93 [Conf]
   
7. Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown
   Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. [Citation Graph (0, 0)][DBLP]
   ISQED, 2005, pp:284-290 [Conf]
   
8. Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown
   Analysis and Optimization of Enhanced MTCMOS Scheme. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2004, pp:234-239 [Conf]
   
9. Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown
   Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:613-623 [Journal]
   
10. 
    Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. [Citation Graph (, )][DBLP]
    
    
11. 
    A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. [Citation Graph (, )][DBLP]
    
    
12. 
    On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. [Citation Graph (, )][DBLP]
    
    
13. 
    On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. [Citation Graph (, )][DBLP]