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Subarnarekha Sinha: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Subarnarekha Sinha, Robert K. Brayton
    Implementation and use of SPFDs in optimizing Boolean networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:103-110 [Conf]
  2. Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton
    Sequential SPFDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:84-90 [Conf]
  3. Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
    Topologically constrained logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:679-686 [Conf]
  4. Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:494-503 [Conf]
  5. Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa
    Optimization of Multi-Valued Multi-Level Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:168-0 [Conf]
  6. Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
    Topologically Constrained Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:13-20 [Conf]
  7. Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    SPFD-based wire removal in standard-cell and network-of-PLA circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1020-1030 [Journal]
  8. Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
    Using simulation and satisfiability to compute flexibilities in Boolean networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:743-755 [Journal]

  9. Automating Logic Rectification by Approximate SPFDs. [Citation Graph (, )][DBLP]


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