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Publications of Author

1. Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel
   Binding, Allocation and Floorplanning in Low Power High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:544-550 [Conf]
   
2. Domenik Helms, Günter Ehmen, Wolfgang Nebel
   Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2006, pp:220-225 [Conf]
   
3. Domenik Helms, Eike Schmidt, Arne Schulz, Ansgar Stammermann, Wolfgang Nebel
   An Improved Power Macro-Model for Arithmetic Datapath Components. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2002, pp:16-24 [Conf]
   
4. Domenik Helms, Marko Hoyer, Wolfgang Nebel
   Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2006, pp:56-65 [Conf]
   
5. Domenik Helms, Eike Schmidt, Wolfgang Nebel
   Leakage in CMOS Circuits - An Introduction. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2004, pp:17-35 [Conf]
   
6. Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel
   A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2005, pp:146-155 [Conf]
   
7. Ansgar Stammermann, Domenik Helms, Milan Schulte, Arne Schulz, Wolfgang Nebel
   Interconnect Driven Low Power High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2003, pp:131-140 [Conf]
   
8. Marko Hoyer, Domenik Helms, Wolfgang Nebel
   Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2007, pp:171-180 [Conf]
   
9. Sven Rosinger, Domenik Helms, Wolfgang Nebel
   RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2007, pp:278-287 [Conf]
   
10. 
    On leakage currents: sources and reduction for transistors, gates, memories and digital systems. [Citation Graph (, )][DBLP]
    
    
11. 
    Voltage- and ABB-island optimization in high level synthesis. [Citation Graph (, )][DBLP]
    
    
12. 
    Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction. [Citation Graph (, )][DBLP]
    
    
13. 
    A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. [Citation Graph (, )][DBLP]