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Koji Nii: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
    Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:398-405 [Conf]
  2. Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino
    A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:73-76 [Conf]
  3. Koji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano
    A low power SRAM using auto-backgate-controlled MT-CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:293-298 [Conf]
  4. Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
    A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:61-66 [Conf]
  5. Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
    A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:107-112 [Conf]

  6. A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. [Citation Graph (, )][DBLP]

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