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Publications of Author

1. Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
   Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:398-405 [Conf]
   
2. Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara
   A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. [Citation Graph (0, 0)][DBLP]
   ICCD, 1993, pp:202-205 [Conf]
   
3. 
   Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. [Citation Graph (, )][DBLP]
   
   
4. 
   Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. [Citation Graph (, )][DBLP]