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Publications of Author

1. Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
   Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:204-209 [Conf]
   
2. Saurabh Goyal, Mihir R. Choudhury, S. S. S. P. Rao, L. Kalyan Kumar
   Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:742-747 [Conf]
   
3. Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
   Design Optimization for Robustness to Single Event Upsets. [Citation Graph (0, 0)][DBLP]
   VTS, 2006, pp:202-207 [Conf]
   
4. Mihir R. Choudhury, Kartik Mohanram
   Accurate and scalable reliability analysis of logic circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:1454-1459 [Conf]
   
5. Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram
   Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:1072-1077 [Conf]
   
6. 
   Technology exploration for graphene nanoribbon FETs. [Citation Graph (, )][DBLP]
   
   
7. 
   Timing-driven optimization using lookahead logic circuits. [Citation Graph (, )][DBLP]
   
   
8. 
   Approximate logic circuits for low overhead, non-intrusive concurrent error detection. [Citation Graph (, )][DBLP]
   
   
9. 
   Masking timing errors on speed-paths in logic circuits. [Citation Graph (, )][DBLP]
   
   
10. 
    TIMBER: Time borrowing and error relaying for online timing error resilience. [Citation Graph (, )][DBLP]
    
    
11. 
    Dominant critical gate identification for power and yield optimization in logic circuits. [Citation Graph (, )][DBLP]