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Gordon R. Chiu:
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- Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. [Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:135-142 [Conf]
- Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. [Citation Graph (0, 0)][DBLP] SLIP, 2006, pp:3-8 [Conf]
- Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:895-903 [Journal]
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