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Publications of Author

1. Sanghyeon Baeg, William A. Rogers
   A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits. [Citation Graph (0, 0)][DBLP]
   ICCD, 1994, pp:354-358 [Conf]
   
2. Sanghyeon Baeg, William A. Rogers
   Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation. [Citation Graph (0, 0)][DBLP]
   ITC, 1994, pp:340-349 [Conf]
   
3. Sung Soo Chung, Sanghyeon Baeg
   AC-JTAG: empowering JTAG beyond testing DC nets. [Citation Graph (0, 0)][DBLP]
   ITC, 2001, pp:30-37 [Conf]
   
4. Sanghyeon Baeg, William A. Rogers
   A cost-effective design for testability: clock line control and test generation using selective clocking. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:850-861 [Journal]
   
5. Sanghyeon Baeg, Sung Soo Chung
   Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:370-383 [Journal]