The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Fu-Chiung Cheng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Li-Kai Chang, Fu-Chiung Cheng
    Automatic Synthesis of Composable Sequential Quantum Boolean Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:289-296 [Conf]
  2. Fu-Chiung Cheng
    Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:301-306 [Conf]
  3. Fu-Chiung Cheng, Shuen-Long Ho
    Efficient Systematic Error-correcting Codes for Semi-Delay-Insensitive Data Transmission. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:24-31 [Conf]
  4. Fu-Chiung Cheng, Huei-Huang Chen, Jiin-Hwai Perng
    Parallel execution on production systems. [Citation Graph (0, 0)][DBLP]
    SPDP, 1990, pp:463-470 [Conf]
  5. Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald, Wen-Chung Cho
    Delay-Insensitive Carry-Lookahead Adders. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:322-328 [Conf]
  6. Fu-Chiung Cheng, Chuin-Ren Wang
    Specification and Design of a Quasi-Delay-Insensitive Java Card. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:356-361 [Conf]
  7. Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:171-176 [Conf]
  8. Fu-Chiung Cheng, Shu-Ming Chang, Chi-Huam Shieh
    Detection and Generation of Self-Timed Pipelines from High Level Specifications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:413-418 [Conf]
  9. Fu-Chiung Cheng, Tai-Chang Hung, Young-Jang Chiou
    Analysis, Design and Implementation of Exception Handling in WWW Services. [Citation Graph (0, 0)][DBLP]
    SOSE, 2006, pp:102-109 [Conf]
  10. Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald
    Self-Timed Carry-Lookahead Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:7, pp:659-672 [Journal]
  11. Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng
    Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:12, pp:1514-1521 [Journal]

  12. Design and Implementation of Software Objects in Hardware. [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002