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Publications of Author

1. Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash G. Chandar
   A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. [Citation Graph (0, 0)][DBLP]
   ICCD, 1999, pp:340-347 [Conf]
   
2. Bhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao
   Enabling Quality and Schedule Predictability in SoC Design using HandoffQC. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:769-774 [Conf]
   
3. Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar
   A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:346-349 [Conf]
   
4. Karthikeyan Madathil, Jagdish C. Rao, Subash G. Chandar, Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar
   A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2000, pp:468-0 [Conf]
   
5. Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji
   Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2002, pp:781-788 [Conf]
   
6. 
   Clock gating for power optimization in ASIC design cycle theory & practice. [Citation Graph (, )][DBLP]
   
   
7. 
   Clock gating effectiveness metrics: Applications to power optimization. [Citation Graph (, )][DBLP]
   
   
8. 
   Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. [Citation Graph (, )][DBLP]