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Dilip K. Bhavsar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard Davies
    Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:180-186 [Conf]
  2. Dilip K. Bhavsar
    "Concatenable Polydividers": Bit-Sliced LFSR Chips for Board Self-Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:88-93 [Conf]
  3. Dilip K. Bhavsar
    An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:768-776 [Conf]
  4. Dilip K. Bhavsar
    An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:311-318 [Conf]
  5. Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson
    Testability access of the high speed test features in the Alpha 21264 microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:487-0 [Conf]
  6. Dilip K. Bhavsar, John H. Edmondson
    Testability Strategy of the ALPHA AXP 21164 Microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:50-59 [Conf]
  7. Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill
    A highly testable and diagnosable fabrication process test chip. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:853-861 [Conf]
  8. Dilip K. Bhavsar, Richard W. Heckelman
    Self-Testing by Polynomial Division. [Citation Graph (0, 0)][DBLP]
    ITC, 1981, pp:208-216 [Conf]
  9. Dilip K. Bhavsar, Balakrishnan Krishnamurthy
    Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ? [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:134-139 [Conf]
  10. Scott Erlanger, Dilip K. Bhavsar, Richard Davies
    Testability Features of the Alpha 21364 Microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:764-772 [Conf]
  11. Dilip K. Bhavsar, Rishan Tan
    Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:385-390 [Conf]
  12. Dilip K. Bhavsar
    Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:94-101 [Conf]
  13. Dilip K. Bhavsar
    A Built-in Self-Test Method for Write-only Content Addressable Memories. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:9-14 [Conf]
  14. Dilip K. Bhavsar, Richard A. Davies
    Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:16-24 [Conf]
  15. Dilip K. Bhavsar
    Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:94-99 [Journal]
  16. Dilip K. Bhavsar
    Testing Interconnections to Static RAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1991, v:8, n:2, pp:63-71 [Journal]
  17. Dilip K. Bhavsar
    ITC 99 Panels. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:4, pp:96-99 [Journal]
  18. Dilip K. Bhavsar, John H. Edmondson
    Alpha 21164 Testability Strategy. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:25-33 [Journal]
  19. Dilip K. Bhavsar, Yervant Zorian
    ITC 97 Panel Sessions. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:7- [Journal]

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