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Michitaka Kameyama: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi
    High-Performance VLSI Processor for Robot Inverse Dynamics Computation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:608-611 [Conf]
  2. Yoshichika Fujioka, Michitaka Kameyama
    2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control. [Citation Graph (0, 0)][DBLP]
    ICRA (3), 1993, pp:149-154 [Conf]
  3. Masanori Hariyama, Michitaka Kameyama
    Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. [Citation Graph (0, 0)][DBLP]
    ICRA, 1998, pp:3691-3696 [Conf]
  4. Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama
    VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. [Citation Graph (0, 0)][DBLP]
    ICRA, 2001, pp:1168-1173 [Conf]
  5. Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama
    Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  6. Y. Nakatani, Masanori Hariyama, Michitaka Kameyama
    Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  7. Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi
    VLSI architecture based on packet data transfer scheme and its application. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1786-1789 [Conf]
  8. Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
    Design of Interconnection-Free Biomolecular Computing System. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:173-180 [Conf]
  9. Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama
    Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:92-97 [Conf]
  10. Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama
    Quaternary Universal-Literal CAM for Cellular Logic Image Processing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:224-229 [Conf]
  11. Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama
    One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:175-0 [Conf]
  12. Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
    Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:382-0 [Conf]
  13. Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
    Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1999, pp:275-279 [Conf]
  14. Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama
    DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:423-429 [Conf]
  15. Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama
    Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1999, pp:30-35 [Conf]
  16. Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, C. Zukeran
    Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:167-172 [Conf]
  17. Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
    Multiple-Valued Dynamic Source-Coupled Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:207-212 [Conf]
  18. Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
    Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:19-26 [Conf]
  19. Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
    Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:64-0 [Conf]
  20. Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama
    Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:134-139 [Conf]
  21. Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama
    Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2003, pp:99-104 [Conf]
  22. Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama
    Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:270-275 [Conf]
  23. Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama
    Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:114-119 [Conf]
  24. Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi
    Residue Arithmetic Based Multiple-Valued VLSI Image Processor. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:330-336 [Conf]
  25. Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
    Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2001, pp:21-26 [Conf]
  26. Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
    Fully Source-Coupled Logic Based Multiple-Valued VLSI. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:270-275 [Conf]
  27. Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama
    Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2000, pp:438-0 [Conf]
  28. Michitaka Kameyama
    Toward the Age of Beyond-Binary Electronics and Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:162-166 [Conf]
  29. Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi
    Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:355-362 [Conf]
  30. Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama
    Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2002, pp:161-0 [Conf]
  31. Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama
    Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:120-125 [Conf]
  32. Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama
    Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:6- [Conf]
  33. Haque Mohammad Munirul, Michitaka Kameyama
    Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:26-30 [Conf]
  34. Haque Mohammad Munirul, Michitaka Kameyama
    Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:328-333 [Conf]
  35. Haque Mohammad Munirul, Michitaka Kameyama
    Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:13- [Conf]
  36. Masami Nakajima, Michitaka Kameyama
    Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:283-288 [Conf]
  37. Masami Nakajima, Michitaka Kameyama
    Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:223-230 [Conf]
  38. Masami Nakajima, Michitaka Kameyama
    Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:104-109 [Conf]
  39. Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
    Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2006, pp:17- [Conf]
  40. M. Ryu, Michitaka Kameyama
    Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:20-0 [Conf]
  41. Saneaki Tamaki, Michitaka Kameyama, Tatsuo Higuchi
    Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:382-388 [Conf]
  42. Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi
    Design of a Multiple-Valued VLSI Processor for Digital Control. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:322-329 [Conf]
  43. Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
    Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:243-248 [Conf]
  44. Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
    Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:46-50 [Conf]
  45. Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama
    High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:95-100 [Conf]
  46. Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama
    Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:258-259 [Conf]
  47. Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi
    Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:193-198 [Conf]
  48. Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
    Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. [Citation Graph (0, 0)][DBLP]
    PRDC, 2000, pp:27-36 [Conf]
  49. Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama
    Architecture of a high-performance stereo vision VLSI processor. [Citation Graph (0, 0)][DBLP]
    Advanced Robotics, 2000, v:14, n:5, pp:329-332 [Journal]
  50. Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
    Interconnection-Free Biomolecular Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:11, pp:41-50 [Journal]
  51. Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi
    A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1988, v:21, n:4, pp:43-56 [Journal]
  52. Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama
    Design and evaluation of a digit-parallel multiple-valued content-addressable memory. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1998, v:29, n:11, pp:48-54 [Journal]
  53. Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama
    A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:2, pp:54-61 [Journal]
  54. Yoshichika Fujioka, Michitaka Kameyama
    Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1999, v:30, n:12, pp:43-51 [Journal]
  55. Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama
    Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1998, v:29, n:11, pp:40-47 [Journal]
  56. Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama
    Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:642-650 [Journal]
  57. Tatsuo Higuchi, Michitaka Kameyama
    Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:12, pp:1212-1221 [Journal]
  58. Michitaka Kameyama, Tatsuo Higuchi
    Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:12, pp:1297-1302 [Journal]
  59. Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi
    High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:34-42 [Journal]
  60. Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi
    Author's Reply. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:5, pp:639- [Journal]

  61. A low-power FPGA based on autonomous fine-grain power-gating. [Citation Graph (, )][DBLP]


  62. Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. [Citation Graph (, )][DBLP]


  63. An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. [Citation Graph (, )][DBLP]


  64. Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. [Citation Graph (, )][DBLP]


  65. Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. [Citation Graph (, )][DBLP]


  66. FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. [Citation Graph (, )][DBLP]


  67. A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. [Citation Graph (, )][DBLP]


  68. FPGA implementation of a vehicle detection algorithm using three-dimensional information. [Citation Graph (, )][DBLP]


  69. Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. [Citation Graph (, )][DBLP]


  70. Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. [Citation Graph (, )][DBLP]


  71. Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. [Citation Graph (, )][DBLP]


  72. Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. [Citation Graph (, )][DBLP]


  73. Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals. [Citation Graph (, )][DBLP]


  74. Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals. [Citation Graph (, )][DBLP]


  75. A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. [Citation Graph (, )][DBLP]


  76. GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. [Citation Graph (, )][DBLP]


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