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Publications of Author

1. W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, P. A. Riocreux, Luis A. Plana
   SPA - A Synthesisable Amulet Core for Smartcard pplications. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2002, pp:201-210 [Conf]
   
2. Z. C. Yu, Stephen B. Furber, Luis A. Plana
   An Investigation into the Security of Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
   ASYNC, 2003, pp:206-215 [Conf]
   
3. W. J. Bainbridge, Luis A. Plana, Stephen B. Furber
   The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:274-279 [Conf]
   
4. Luis A. Plana, Sam Taylor, Doug Edwards
   Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. [Citation Graph (0, 0)][DBLP]
   ICCD, 2005, pp:703-710 [Conf]
   
5. Luis A. Plana, Steven M. Nowick
   Concurrency-oriented optimization for low-power asynchronous systems. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1996, pp:151-156 [Conf]
   
6. Luis A. Plana, P. A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu
   SPA - a secure Amulet core for smartcard applications. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2003, v:27, n:9, pp:431-446 [Journal]
   
7. Luis A. Plana, Doug Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley
   Performance-driven syntax-directed synthesis of asynchronous processors. [Citation Graph (0, 0)][DBLP]
   CASES, 2007, pp:43-47 [Conf]
   
8. Luis A. Plana, Steven M. Nowick
   Architectural optimization for low-power nonpipelined asynchronous systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:56-65 [Journal]
   
9. 
   An admission control system for QoS provision on a best-effort GALS interconnect. [Citation Graph (, )][DBLP]
   
   
10. 
    Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system. [Citation Graph (, )][DBLP]
    
    
11. 
    SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network. [Citation Graph (, )][DBLP]
    
    
12. 
    Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker. [Citation Graph (, )][DBLP]
    
    
13. 
    A communication infrastructure for a million processor machine. [Citation Graph (, )][DBLP]
    
    
14. 
    A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor. [Citation Graph (, )][DBLP]
    
    
15. 
    SpiNNaker: The Design Automation Problem. [Citation Graph (, )][DBLP]
    
    
16. 
    Understanding the interconnection network of SpiNNaker. [Citation Graph (, )][DBLP]
    
    
17. 
    SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. [Citation Graph (, )][DBLP]
    
    
18. 
    Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric. [Citation Graph (, )][DBLP]
    
    
19. 
    Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware. [Citation Graph (, )][DBLP]
    
    
20. 
    An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. [Citation Graph (, )][DBLP]
    
    
21. 
    A GALS Infrastructure for a Massively Parallel Multiprocessor. [Citation Graph (, )][DBLP]