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Publications of Author

1. Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl
   On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. [Citation Graph (0, 0)][DBLP]
   ICCD, 2001, pp:214-220 [Conf]
   
2. Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan
   Optimal Sequencing Energy Allocation for CMOS Integrated Systems. [Citation Graph (0, 0)][DBLP]
   ISQED, 2002, pp:194-199 [Conf]
   
3. 
   A 65-nm pulsed latch with a single clocked transistor. [Citation Graph (, )][DBLP]
   
   
4. 
   A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. [Citation Graph (, )][DBLP]
   
   
5. 
   Cache Design for Low Power and High Yield. [Citation Graph (, )][DBLP]