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Publications of Author

1. Jayashree Saxena, Dhiraj K. Pradhan
   Desgin for Testability of Asynchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   ICCD, 1993, pp:518-522 [Conf]
   
2. Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Jones, Jayashree Saxena
   Integrating Automated Diagnosis into the Testing and Failure Analysis Operations. [Citation Graph (0, 0)][DBLP]
   ITC, 1996, pp:934- [Conf]
   
3. Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington
   Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:355-364 [Conf]
   
4. David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler
   Bridging Fault Diagnosis in the Absence of Physical Information. [Citation Graph (0, 0)][DBLP]
   ITC, 1997, pp:887-893 [Conf]
   
5. Jayashree Saxena
   IC diagnosis: preventing wars and war stories. [Citation Graph (0, 0)][DBLP]
   ITC, 1998, pp:1138- [Conf]
   
6. Jayashree Saxena, Kenneth M. Butler
   An empirical study on the effects of test type ordering on overall test efficiency. [Citation Graph (0, 0)][DBLP]
   ITC, 2000, pp:408-416 [Conf]
   
7. Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess
   On applying non-classical defect models to automated diagnosis. [Citation Graph (0, 0)][DBLP]
   ITC, 1998, pp:748-757 [Conf]
   
8. Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech
   Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges . [Citation Graph (0, 0)][DBLP]
   ITC, 2002, pp:1120-1129 [Conf]
   
9. Jayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger
   A Case Study of IR-Drop in Structured At-Speed Testing. [Citation Graph (0, 0)][DBLP]
   ITC, 2003, pp:1098-1104 [Conf]
   
10. Jayashree Saxena, Kenneth M. Butler, Lee Whetsel
    An analysis of power reduction techniques in scan testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:670-677 [Conf]
    
11. Jayashree Saxena, Dhiraj K. Pradhan
    A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:724-733 [Conf]
    
12. Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler
    Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:729-738 [Conf]
    
13. Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Kinra, Jayashree Saxena
    Automated Diagnosis in Testing and Failure Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:3, pp:83-89 [Journal]
    
14. Dhiraj K. Pradhan, Jayashree Saxena
    A novel scheme to reduce test application time in circuits with full scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1577-1586 [Journal]
    
15. 
    Multidimensional Test Escape Rate Modeling. [Citation Graph (, )][DBLP]