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Charles R. Moore: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- C. R. Moore, D. M. Balser, J. S. Muhich, R. E. East
IBM Single Chip RISC Processor (RSC). [Citation Graph (0, 0)][DBLP]
ICCD, 1992, pp:200-204 [Conf] - Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger
Exploiting Microarchitectural Redundancy For Defect Tolerance. [Citation Graph (0, 0)][DBLP]
ICCD, 2003, pp:481-488 [Conf] - Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
ISCA, 2003, pp:422-433 [Conf] - Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger
Microprocessor pipeline energy analysis. [Citation Graph (0, 0)][DBLP]
ISLPED, 2003, pp:282-287 [Conf] - Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
Scalable Hardware Memory Disambiguation for High ILP Processors. [Citation Graph (0, 0)][DBLP]
MICRO, 2003, pp:399-410 [Conf] - Charles R. Moore, Russell C. Stanphill
The PowerPC Alliance. [Citation Graph (0, 0)][DBLP]
Commun. ACM, 1994, v:37, n:6, pp:25-27 [Journal] - Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode
Scaling to the End of Silicon with EDGE Architectures. [Citation Graph (0, 0)][DBLP]
IEEE Computer, 2004, v:37, n:7, pp:44-55 [Journal] - Charles R. Moore
Managing the Transition from Complexity to Elegance: Knowing When You Have a Problem. [Citation Graph (0, 0)][DBLP]
IEEE Micro, 2003, v:23, n:5, pp:88-87 [Journal] - Charles R. Moore
Managing the Transition from Complexity to Elegance: Design Convergence. [Citation Graph (0, 0)][DBLP]
IEEE Micro, 2004, v:24, n:1, pp:80- [Journal] - Charles R. Moore, Kevin W. Rudd, Ruby B. Lee, Pradip Bose
Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences. [Citation Graph (0, 0)][DBLP]
IEEE Micro, 2003, v:23, n:6, pp:8-10 [Journal] - Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
Scalable Hardware Memory Disambiguation for High-ILP Processors. [Citation Graph (0, 0)][DBLP]
IEEE Micro, 2004, v:24, n:6, pp:118-127 [Journal] - Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
IEEE Micro, 2003, v:23, n:6, pp:46-51 [Journal] - Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. [Citation Graph (0, 0)][DBLP]
TACO, 2004, v:1, n:1, pp:62-93 [Journal]
Microarchitecture in the system-level integration era. [Citation Graph (, )][DBLP]
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