The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Charles R. Moore: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. C. R. Moore, D. M. Balser, J. S. Muhich, R. E. East
    IBM Single Chip RISC Processor (RSC). [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:200-204 [Conf]
  2. Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger
    Exploiting Microarchitectural Redundancy For Defect Tolerance. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:481-488 [Conf]
  3. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
    Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:422-433 [Conf]
  4. Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger
    Microprocessor pipeline energy analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:282-287 [Conf]
  5. Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
    Scalable Hardware Memory Disambiguation for High ILP Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:399-410 [Conf]
  6. Charles R. Moore, Russell C. Stanphill
    The PowerPC Alliance. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1994, v:37, n:6, pp:25-27 [Journal]
  7. Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode
    Scaling to the End of Silicon with EDGE Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:7, pp:44-55 [Journal]
  8. Charles R. Moore
    Managing the Transition from Complexity to Elegance: Knowing When You Have a Problem. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:88-87 [Journal]
  9. Charles R. Moore
    Managing the Transition from Complexity to Elegance: Design Convergence. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:1, pp:80- [Journal]
  10. Charles R. Moore, Kevin W. Rudd, Ruby B. Lee, Pradip Bose
    Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:8-10 [Journal]
  11. Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
    Scalable Hardware Memory Disambiguation for High-ILP Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:118-127 [Journal]
  12. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
    Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:46-51 [Journal]
  13. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore
    TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:1, pp:62-93 [Journal]

  14. Microarchitecture in the system-level integration era. [Citation Graph (, )][DBLP]


Search in 0.178secs, Finished in 0.179secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002