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Payman Zarkesh-Ha: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Payman Zarkesh-Ha, Ken Doniger, William Loh, Dechang Sun, Rick Stephani, Gordon Priebe
    A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:84-89 [Conf]
  2. Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright
    Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:405-409 [Conf]
  3. Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix
    Prediction of interconnect adjacency distribution: derivation, validation, and applications. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:99-106 [Conf]
  4. Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl
    Prediction of interconnect fan-out distribution using Rent's rule. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:107-112 [Conf]
  5. Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright
    Prediction of interconnect pattern density distribution: derivation, validation, and applications. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:85-91 [Conf]
  6. James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:123-127 [Conf]
  7. James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl
    Interconnect opportunities for gigascale integration. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:245-264 [Journal]
  8. James W. Joyner, Payman Zarkesh-Ha, James D. Meindl
    Global interconnect design in a three-dimensional system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:367-372 [Journal]
  9. Payman Zarkesh-Ha, Ken Doniger
    Stochastic interconnect layout sensitivity model. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:9-14 [Conf]
  10. Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl
    A compact physical via blockage model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:689-692 [Journal]
  11. Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:649-659 [Journal]
  12. James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Impact of three-dimensional architectures on interconnects in gigascale integration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:922-928 [Journal]

  13. Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model. [Citation Graph (, )][DBLP]


  14. Analytical Noise-Rejection Model Based on Short Channel MOSFET. [Citation Graph (, )][DBLP]


  15. A robust and low power dual data rate (DDR) flip-flop using c-elements. [Citation Graph (, )][DBLP]


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