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John A. Darringer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John A. Darringer, Daniel Brand, William H. Joyner Jr., Louise Trevillyan, John V. Gerbi
    Production logic synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer Science, 1985, pp:13-16 [Conf]
  2. Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal
    SEAS: a system for early analysis of SoCs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:150-155 [Conf]
  3. John A. Darringer
    Where in the World Should CAD Software be Made? (Panel Abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:742- [Conf]
  4. Shishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon
    Were the good old days all that good?: EDA then and now. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:543- [Conf]
  5. Steven E. Schulz, Georgia Marszalek, Greg Hinckley, Greg Spirakis, Karen Vahtra, John A. Darringer, J. George Janac, Handel H. Jones
    Panel: What Drives EDA Innovation? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:790-791 [Conf]
  6. Jeff Parkhurst, John A. Darringer, Bill Grundmann
    From single core to multi-core: preparing for a new exponential. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:67-72 [Conf]
  7. John A. Darringer
    Advanced Design Automation in Industry. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:527- [Conf]
  8. Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin
    A Mask Reuse Methodology for Reducing System-on-a-Chip Cost. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:482-487 [Conf]
  9. John A. Darringer
    Automated Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Engineering, 1984, pp:177-186 [Conf]
  10. John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin
    Early analysis tools for system-on-a-chip design. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:6, pp:691-708 [Journal]
  11. John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan
    LSS: A system for production logic synthesis. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2000, v:44, n:1, pp:157-166 [Journal]
  12. John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan
    LSS: A System for Production Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1984, v:28, n:5, pp:537-545 [Journal]
  13. John A. Darringer, William H. Joyner Jr., C. Leonard Berman, Louise Trevillyan
    Logic Synthesis Through Local Transformations. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1981, v:25, n:4, pp:272-280 [Journal]
  14. John A. Darringer, Evan Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich Schanzenbach, Gustavo Tellez, Louise Trevillyan
    EDA in IBM: past, present, and future. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1476-1497 [Journal]
  15. John A. Darringer
    Multi-Core Design Automation Challenges. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:760-764 [Conf]

  16. Exploring power management in multi-core systems. [Citation Graph (, )][DBLP]


  17. Performance modeling for early analysis of multi-core systems. [Citation Graph (, )][DBLP]


  18. Power-efficient, reliable microprocessor architectures: modeling and design methods. [Citation Graph (, )][DBLP]


  19. Thousand-Core Chips [Roundtable]. [Citation Graph (, )][DBLP]


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