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Daniel Brand: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Daniel Brand, Pitro Zafiropulo
    On Communicating Finite-State Machines [Citation Graph (3, 0)][DBLP]
    J. ACM, 1983, v:30, n:2, pp:323-342 [Journal]
  2. John A. Darringer, Daniel Brand, William H. Joyner Jr., Louise Trevillyan, John V. Gerbi
    Production logic synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer Science, 1985, pp:13-16 [Conf]
  3. William H. Joyner Jr., Louise Trevillyan, Daniel Brand, Theresa A. Nix, Steven C. Gundersen
    Technology adaption in logic synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:94-100 [Conf]
  4. Daniel Brand
    Proving Programs Incorrect. [Citation Graph (0, 0)][DBLP]
    ICALP, 1976, pp:201-227 [Conf]
  5. Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, S. Prakash
    Efficient use of large don't cares in high-level and logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:272-278 [Conf]
  6. Daniel Brand
    Exhaustive simulation need not require an exponential number of tests. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:98-101 [Conf]
  7. Daniel Brand
    Verification of large synthesized designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:534-537 [Conf]
  8. Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
    Be careful with don't cares. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:83-86 [Conf]
  9. Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain
    Incremental synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:14-18 [Conf]
  10. Daniel Brand, Chandramouli Visweswariah
    Inaccuracies in power estimation during logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:388-394 [Conf]
  11. Daniel Brand, Robert F. Damiano, Lukas P. P. P. van Ginneken, Anthony D. Drumm
    In the Driver's Seat of BooleDozer. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:518-521 [Conf]
  12. Daniel Brand, Vijay S. Iyengar
    Identification of Single Gate Delay Fault Redundancies. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:24-28 [Conf]
  13. Daniel Brand
    A Software Falsifier. [Citation Graph (0, 0)][DBLP]
    ISSRE, 2000, pp:174-185 [Conf]
  14. Daniel Brand, Vijay S. Iyengar
    Synthesis of Pseudo-Random Pattern Testable Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:501-508 [Conf]
  15. William H. Joyner Jr., William C. Carter, Daniel Brand
    Using Machine Descriptions in Program Verification. [Citation Graph (0, 0)][DBLP]
    Jerusalem Conference on Information Technology, 1978, pp:515-522 [Conf]
  16. Daniel Brand
    Analytic Resolution in Theorem Proving. [Citation Graph (0, 0)][DBLP]
    Artif. Intell., 1976, v:7, n:4, pp:285-318 [Journal]
  17. Daniel Brand, William H. Joyner Jr.
    Verification of Protocols Using Symbolic Execution. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 1978, v:2, n:, pp:351-360 [Journal]
  18. John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin
    Early analysis tools for system-on-a-chip design. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:6, pp:691-708 [Journal]
  19. John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan
    LSS: A system for production logic synthesis. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2000, v:44, n:1, pp:157-166 [Journal]
  20. John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan
    LSS: A System for Production Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1984, v:28, n:5, pp:537-545 [Journal]
  21. Daniel Brand
    Path Calculus in Program Verification. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1978, v:25, n:4, pp:630-651 [Journal]
  22. Daniel Brand
    Proving Theorems with the Modification Method. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1975, v:4, n:4, pp:412-430 [Journal]
  23. Daniel Brand
    Redundancy and Don't Cares in Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:10, pp:947-952 [Journal]
  24. Daniel Brand
    Detecting Sneak Paths in Transistor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:3, pp:274-278 [Journal]
  25. Daniel Brand, Vijay S. Iyengar
    Timing Analysis Using Functional Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:10, pp:1309-1315 [Journal]
  26. Daniel Brand, Tsutomu Sasao
    Minimization of AND-EXOR Expressions Using Rewrite Rules. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:5, pp:568-576 [Journal]
  27. Daniel Brand
    Exhaustive simulation need not require an exponential number of tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1635-1641 [Journal]
  28. Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
    Don't cares in synthesis: theoretical pitfalls and practical solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:285-304 [Journal]
  29. Daniel Brand, Vijay S. Iyengar
    Identification of redundant delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:553-565 [Journal]

  30. Evidence-Based Analysis and Inferring Preconditions for Bug Detection. [Citation Graph (, )][DBLP]


  31. Flexible pointer analysis using assign-fetch graphs. [Citation Graph (, )][DBLP]


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