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Sujit Dey: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sujit Dey, Pradip K. Srimani
    Parallel VLSI computation of all shortest paths in a graph. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer Science, 1988, pp:373-379 [Conf]
  2. Sujit Dey, Anand Raghunathan, Rabindra K. Roy
    Considering Testability during High-level Design (Embedded Tutorial). [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:205-210 [Conf]
  3. Kanishka Lahiri, Sujit Dey, Debashis Panigrahi, Anand Raghunathan
    Battery-Driven System Design: A New Frontier in Low Power Design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:261-267 [Conf]
  4. Luciano Lavagno, Sujit Dey, Rajesh Gupta
    Specification, Modeling and Design Tools for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:21-23 [Conf]
  5. Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
    Synthesis-for-testability using transformations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  6. Debashis Panigrahi, Clark N. Taylor, Sujit Dey
    A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:553-560 [Conf]
  7. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Fast system-level power profiling for battery-efficient system design. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:157-162 [Conf]
  8. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    A case study on modeling shared memory access effects during performance analysis of HW/SW systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:117-121 [Conf]
  9. Xiaoliang Bai, Sujit Dey, Janusz Rajski
    Self-test methodology for at-speed test of crosstalk in chip interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:619-624 [Conf]
  10. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Clock Period Optimization During Resource Sharing and Assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:195-200 [Conf]
  11. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:491-496 [Conf]
  12. Srimat T. Chakradhar, Sujit Dey
    Resynthesis and Retiming for Optimum Partial Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:87-93 [Conf]
  13. Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler
    Sequential Circuit Delay optimization Using Global Path Delays. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:483-489 [Conf]
  14. Li Chen, Xiaoliang Bai, Sujit Dey
    Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:317-320 [Conf]
  15. Li Chen, Sujit Dey
    Software-based diagnosis for processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:259-262 [Conf]
  16. Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng
    Embedded hardware and software self-testing methodologies for processor cores. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:625-630 [Conf]
  17. Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey
    A scalable software-based self-test methodology for programmable processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:548-553 [Conf]
  18. Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy
    Test challenges for deep sub-micron technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:142-149 [Conf]
  19. Sujit Dey, Franc Brglez, Gershon Kedem
    Corolla Based Circuit Partitioning and Resynthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:607-612 [Conf]
  20. Indradeep Ghosh, Sujit Dey, Niraj K. Jha
    A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:542-547 [Conf]
  21. Zia Iqbal, Miodrag Potkonjak, Sujit Dey, Alice C. Parker
    Critical Path Minimization Using Retiming and Algebraic Speed-Up. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:573-577 [Conf]
  22. Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh Rao
    On-Chip Communication Architecture for OC-768 Network Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:678-683 [Conf]
  23. Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
    Embedded software-based self-testing for SoC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:355-360 [Conf]
  24. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Communication architecture based power management for battery efficient system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:691-696 [Conf]
  25. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
    Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:513-518 [Conf]
  26. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-Case Computation: A High-Level Technique for Power and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:56-61 [Conf]
  27. Miodrag Potkonjak, Sujit Dey
    Optimizing Resource Utilization and Testability Using Hot Potato Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:201-205 [Conf]
  28. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    Glitch Analysis and Reduction in Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:331-336 [Conf]
  29. Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
    Power Management Techniques for Control-Flow Intensive Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:429-434 [Conf]
  30. Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:571-574 [Conf]
  31. Clark N. Taylor, Sujit Dey, Yi Zhao
    Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:754-757 [Conf]
  32. Kenneth D. Wagner, Sujit Dey
    High-Level Synthesis for Testability: A Survey and Perspective. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:131-136 [Conf]
  33. Chong Zhao, Xiaoliang Bai, Sujit Dey
    A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:894-899 [Conf]
  34. Chong Zhao, Yi Zhao, Sujit Dey
    Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:190-195 [Conf]
  35. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
    Efficient Power Co-Estimation Techniques for System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:27-34 [Conf]
  36. Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:728-733 [Conf]
  37. Saumya Chandra, Sujit Dey
    Addressing Computational and Networking Constraints to Enable Video Streaming from Wireless Appliances. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:27-32 [Conf]
  38. Dong-Gi Lee, Sujit Dey
    Addressing Server Latency and Capacity to Enable Fast and Affordable Wireless Image Data Services. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2003, pp:40-47 [Conf]
  39. Pranav Ashar, Sujit Dey, Sharad Malik
    Exploiting multi-cycle false paths in the performance optimization of sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:510-517 [Conf]
  40. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Provably correct high-level timing analysis without path sensitization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:736-742 [Conf]
  41. Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao
    Fault modeling and simulation for crosstalk in system-on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:297-303 [Conf]
  42. Sujit Dey, Jacob A. Abraham, Yervant Zorian
    High-level design validation and test. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:3- [Conf]
  43. Sujit Dey, Surendra Bommu
    Performance analysis of a system of communicating processes. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:590-597 [Conf]
  44. Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
    A controller-based design-for-testability technique for controller-data path circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:534-540 [Conf]
  45. Sujit Dey, Miodrag Potkonjak
    Non-scan design-for-testability of RT-level data paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:640-645 [Conf]
  46. Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler
    Performance optimization of sequential circuits by eliminating retiming bottlenecks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:504-509 [Conf]
  47. Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy
    Exploiting hardware sharing in high-level synthesis for partial scan optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:20-25 [Conf]
  48. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Efficient Exploration of the SoC Communication Architecture Design Space. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:424-430 [Conf]
  49. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Fast performance analysis of bus-based system-on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:566-573 [Conf]
  50. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Transforming control-flow intensive designs to facilitate power management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:657-664 [Conf]
  51. Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi
    Design-for-debugging of application specific designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:295-301 [Conf]
  52. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    Register-transfer level estimation techniques for switching activity and power consumption. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:158-165 [Conf]
  53. Krishna Sekar, Kanishka Lahiri, Sujit Dey
    Dynamic Platform Management for Configurable Platform-Based System-on-Chips. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:641-649 [Conf]
  54. Yervant Zorian, Sujit Dey, Mike Rodgers
    Test of Future System-on-Chips. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:392-398 [Conf]
  55. Sujit Dey, Franc Brglez, Gershon Kedem
    Partitioning Sequential Circuits for Logic Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:70-76 [Conf]
  56. Miodrag Potkonjak, Sujit Dey, Zia Iqbal, Alice C. Parker
    High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:498-504 [Conf]
  57. Yi Zhao, Sujit Dey
    Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:7-11 [Conf]
  58. Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
    Controller re-specification to minimize switching activity in controller/data path circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:301-304 [Conf]
  59. Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Considering process variations during system-level power analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:342-345 [Conf]
  60. Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas
    Noise-Aware Driver Modeling for Nanometer Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:177-182 [Conf]
  61. Chong Zhao, Sujit Dey
    Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO). [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:133-140 [Conf]
  62. Toshiharu Asaka, Masaaki Yoshida, Subhrajit Bhattacharya, Sujit Dey
    H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:265-274 [Conf]
  63. Xiaoliang Bai, Sujit Dey, Angela Krstic
    HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:112-121 [Conf]
  64. Sujit Dey, Miodrag Potkonjak
    Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:184-193 [Conf]
  65. Indradeep Ghosh, Niraj K. Jha, Sujit Dey
    A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:50-59 [Conf]
  66. Yi Zhao, Li Chen, Sujit Dey
    On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:491-499 [Conf]
  67. Yi Zhao, Sujit Dey
    Analysis of interconnect crosstalk defect coverage of test sets. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:492-501 [Conf]
  68. Yervant Zorian, Erik Jan Marinissen, Sujit Dey
    Testing embedded-core based system chips. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:130-0 [Conf]
  69. Clark N. Taylor, Debashis Panigrahi, Sujit Dey
    Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication. [Citation Graph (0, 0)][DBLP]
    Embedded Processor Design Challenges, 2002, pp:260-273 [Conf]
  70. Sujit Dey, Franc Brglez, Gershon Kedem
    Identification and Resynthesis of Pipelines in Sequential Networks. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:439-449 [Conf]
  71. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Performance Analysis of Systems with Multi-Channel Communication Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:530-537 [Conf]
  72. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:29-35 [Conf]
  73. Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi
    Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:261-267 [Conf]
  74. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    A Power Management Methodology for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:24-19 [Conf]
  75. Luciano Lavagno, Sujit Dey, Rajesh K. Gupta
    Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:21-23 [Conf]
  76. Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan
    Battery Life Estimation of Mobile Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:57-63 [Conf]
  77. Debashis Panigrahi, Clark N. Taylor, Sujit Dey
    A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:553-0 [Conf]
  78. Anand Raghunathan, Sujit Dey
    Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:9-10 [Conf]
  79. Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
    Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:193-198 [Conf]
  80. Kaushik Roy, Anand Raghunathan, Sujit Dey
    Low Power Design Methodologies for Systems-on-Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:609- [Conf]
  81. Krishna Sekar, Kanishka Lahiri, Sujit Dey
    Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:307-0 [Conf]
  82. Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey
    High-level Synthesis of Multi-process Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:467-473 [Conf]
  83. Subhrajit Bhattacharya, Sujit Dey
    H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:74-80 [Conf]
  84. Xiaoliang Bai, Sujit Dey
    High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:169-177 [Conf]
  85. Li Chen, Sujit Dey
    DEFUSE: A Deterministic Functional Self-Test Methodology for Processors. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:255-262 [Conf]
  86. C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim
    Validation and Test of Network Processors and ASICs. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:407-410 [Conf]
  87. Krishna Sekar, Sujit Dey
    LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:417-422 [Conf]
  88. Sujit Dey, Pradip K. Srimani
    A New Parallel Sorting Algorithm and its Efficient VLSI Implementation. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1990, v:33, n:3, pp:241-246 [Journal]
  89. Yervant Zorian, Erik Jan Marinissen, Sujit Dey
    Testing Embedded-Core-Based System Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:6, pp:52-60 [Journal]
  90. Sujit Dey, Debashis Panigrahi, Li Chen, Clark N. Taylor, Krishna Sekar, Pablo Sanchez
    Using a Soft Core in a SoC Design: Experiences with picoJava. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:3, pp:60-71 [Journal]
  91. Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
    Embedded Software-Based Self-Test for Programmable Core-Based Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:4, pp:18-27 [Journal]
  92. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Communication-Based Power Management. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:4, pp:118-130 [Journal]
  93. Chong Zhao, Sujit Dey, Xiaoliang Bai
    Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:362-375 [Journal]
  94. Faraydon Karim, Anh Nguyen, Sujit Dey
    An Interconnect Architecture for Networking Systems on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:5, pp:36-45 [Journal]
  95. Naomi Ramos, Debashis Panigrahi, Sujit Dey
    Quality of service provisioning in 802.11e networks: challenges, approaches, and future directions. [Citation Graph (0, 0)][DBLP]
    IEEE Network, 2005, v:19, n:4, pp:14-20 [Journal]
  96. Pranav Ashar, Sujit Dey, Sharad Malik
    Exploiting multicycle false paths in the performance optimization of sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1067-1075 [Journal]
  97. Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas
    Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1256-1263 [Journal]
  98. Xiaoliang Bai, Sujit Dey
    High-level crosstalk defect Simulation methodology for system-on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:9, pp:1355-1361 [Journal]
  99. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Fast true delay estimation during high level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1088-1105 [Journal]
  100. Srimat T. Chakradhar, Sujit Dey
    Resynthesis and retiming for optimum partial scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:5, pp:621-630 [Journal]
  101. Li Chen, Sujit Dey
    Software-based self-testing methodology for processor cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:369-380 [Journal]
  102. Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
    A controller redesign technique to enhance testability of controller-data path circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:157-168 [Journal]
  103. Sujit Dey, Miodrag Potkonjak
    Nonscan design-for-testability techniques using RT-level design information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:12, pp:1488-1506 [Journal]
  104. Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi
    Controller-based power management for control-flow intensive designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1496-1508 [Journal]
  105. Indradeep Ghosh, Sujit Dey, Niraj K. Jha
    A fast and low-cost testing technique for core-based system-chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:863-877 [Journal]
  106. Indradeep Ghosh, Niraj K. Jha, Sujit Dey
    A low overhead design for testability and test generation technique for core-based systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1661-1676 [Journal]
  107. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    System-level performance analysis for designing on-chipcommunication architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:768-783 [Journal]
  108. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Efficient power profiling for battery-driven embedded system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:919-932 [Journal]
  109. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Design space exploration for optimizing on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:952-961 [Journal]
  110. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
    Design of high-performance system-on-chips using communication architecture tuners. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:620-636 [Journal]
  111. Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey
    Common-case computation: a high-level energy and performance optimization technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:33-49 [Journal]
  112. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    Register transfer level power optimization with emphasis on glitch analysis and reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1114-1131 [Journal]
  113. Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
    Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:531-546 [Journal]
  114. Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
    Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1141-1154 [Journal]
  115. Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Resource budgeting for Multiprocess High-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:7, pp:1010-1019 [Journal]
  116. Jennifer L. Wong, Miodrag Potkonjak, Sujit Dey
    Optimizing designs using the addition of deflection operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:50-59 [Journal]
  117. Yi Zhao, Sujit Dey
    Fault-coverage analysis techniques of crosstalk in chip interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:770-782 [Journal]
  118. Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
    Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:2, pp:285-307 [Journal]
  119. Yi Zhao, Sujit Dey, Li Chen
    Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:7, pp:746-755 [Journal]
  120. Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    System-on-Chip Power Management Considering Leakage Power Variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:877-882 [Conf]
  121. Subhrajit Bhattacharya, Franc Brglez, Sujit Dey
    Transformations and resynthesis for testability of RT-level control-data path specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:3, pp:304-318 [Journal]
  122. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey
    Power management in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:7-15 [Journal]
  123. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
    Cosimulation-based power estimation for system-on-chip design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:253-266 [Journal]
  124. Anand Raghunathan, Sujit Dey, Niraj K. Jha
    High-level macro-modeling and estimation techniques for switching activity and power consumption. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:538-557 [Journal]
  125. Naomi Ramos, Debashis Panigrahi, Sujit Dey
    Dynamic adaptation policies to improve quality of service of real-time multimedia applications in IEEE 802.11e WLAN Networks. [Citation Graph (0, 0)][DBLP]
    Wireless Networks, 2007, v:13, n:4, pp:511-535 [Journal]

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  127. Modeling soft error effects considering process variations. [Citation Graph (, )][DBLP]


  128. Coping with Variations through System-Level Design. [Citation Graph (, )][DBLP]


  129. Joint Computation and Communication Scheduling to Enable Rich Mobile Applications. [Citation Graph (, )][DBLP]


  130. Modeling and Characterizing User Experience in a Cloud Server Based Mobile Gaming Approach. [Citation Graph (, )][DBLP]


  131. Addressing Response Time and Video Quality in Remote Server Based Internet Mobile Gaming. [Citation Graph (, )][DBLP]


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