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Author:
Magdy A. Bayoumi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Khaled M. Elleithy, Magdy A. Bayoumi
    A Framework for High Level Synthesis of Digital Architectures from U-Recursive Algorithms. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer Science, 1990, pp:305-311 [Conf]
  2. Wael M. Badawy, Magdy A. Bayoumi
    A Multiplication-Free Parallel Architecture for Affine Transformation. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:25-34 [Conf]
  3. Ahmed M. Shams, Magdy A. Bayoumi
    A 108 Gbps, 1.5 GHz 1D-DCT Architecture. [Citation Graph (0, 0)][DBLP]
    ASAP, 2000, pp:163-172 [Conf]
  4. Ruth Aguilar-Ponce, Ashok Kumar, J. Luis Tecpanecatl-Xihuitl, Magdy A. Bayoumi
    An Architecture for Automated Scene Understanding. [Citation Graph (0, 0)][DBLP]
    CAMP, 2005, pp:19-24 [Conf]
  5. Beth Wilson, Magdy A. Bayoumi
    Compressed-Domain Classification of Texture Images. [Citation Graph (0, 0)][DBLP]
    CAMP, 2000, pp:347-355 [Conf]
  6. Nan Wang, Magdy A. Bayoumi
    Fraction Control Bus: A New SoC On-chip Communication Architecture Design. [Citation Graph (0, 0)][DBLP]
    ESA, 2005, pp:124-129 [Conf]
  7. Peiyi Zhao, Tarek Darwish, Magdy A. Bayoumi
    Low Power Conditional-Discharge Pulsed Flip-Flops. [Citation Graph (0, 0)][DBLP]
    Embedded Systems and Applications, 2003, pp:204-209 [Conf]
  8. Hanan A. Mahmoud, Magdy A. Bayoumi
    An Efficient Low-Bit Rate Motion Compensation Technique Based on Quadtree. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 2000, pp:560- [Conf]
  9. Hanan A. Mahmoud, Magdy A. Bayoumi
    An Efficient Successive Elimination Algorithm for Block-Matching Motion Estimation. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 2000, pp:559- [Conf]
  10. Beth Wilson, Magdy A. Bayoumi
    Compressed Domain Texture Classification from a Modified EZW Symbol Stream. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 2000, pp:579- [Conf]
  11. Hanan A. Mahmoud, Magdy A. Bayoumi
    An Efficient Low-Bit Rate Adaptive Mesh-Based Motion Compensation Technique. [Citation Graph (0, 0)][DBLP]
    Workshop on Digital and Computational Video, 2001, pp:164-172 [Conf]
  12. Ahmed M. Shams, Mohamed A. Elgamel, Magdy A. Bayoumi
    Hybrid Mesh-Based/Block-Based Motion Compensation Architecture. [Citation Graph (0, 0)][DBLP]
    Workshop on Digital and Computational Video, 2001, pp:194-201 [Conf]
  13. Rafic A. Ayoubi, Haissam Ziade, Magdy A. Bayoumi
    Fault Tolerant Hopfield Associative Memory on Torus. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:369-376 [Conf]
  14. A. Agrawal, A. Raju, S. Varadarajan, Magdy A. Bayoumi
    A scalable shared buffer ATM switch architecture. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:256-261 [Conf]
  15. B. A. Alhalabi, Magdy A. Bayoumi
    A scalable analog architecture for neural networks with on-chip learning and refreshing. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:33-0 [Conf]
  16. Raghava V. Cherabuddi, Magdy A. Bayoumi, H. Krishnamurthy
    A low power based system partitioning and binding technique for multi-chip module architectures. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:156-162 [Conf]
  17. Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi
    Noise tolerant low voltage XOR-XNOR for fast arithmetic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:285-288 [Conf]
  18. Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi
    Noise-tolerant high fan-in dynamic CMOS circuit design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:134-137 [Conf]
  19. Ahmed M. Shams, Magdy A. Bayoumi
    A New Full Adder Cell for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:45-0 [Conf]
  20. Paul Shipley, Sherif Sayed, Magdy A. Bayoumi
    A High Speed VLSI Architecture for Scaleable ATM Switches. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:72-76 [Conf]
  21. Michael Weeks, M. B. Maaz, H. Krishnamurthy, Paul Shipley, Magdy A. Bayoumi
    A prototype chipset for a large scaleable ATM switching node. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:131-136 [Conf]
  22. A. Agrawal, Magdy A. Bayoumi, A. Elchouemi
    A new ATM congestion control scheme for shared buffer switch architectures. [Citation Graph (0, 0)][DBLP]
    ICCCN, 1995, pp:604- [Conf]
  23. Wael M. Badawy, Magdy A. Bayoumi
    Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:533-536 [Conf]
  24. Ashok Kumar, Magdy A. Bayoumi
    Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:321-324 [Conf]
  25. Yijun Li, Hongyi Wu, Dmitri D. Perkins, Nian-Feng Tzeng, Magdy A. Bayoumi
    MAC-SCC: Medium Access Control with a Separate Control Channel for Multihop Wireless Networks. [Citation Graph (0, 0)][DBLP]
    ICDCS Workshops, 2003, pp:764-769 [Conf]
  26. Hanan A. Mahmoud, Magdy A. Bayoumi
    A New Block-Matching Motion Estimation Algorithm Based on Successive Elimination. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  27. Hanan A. Mahmoud, Magdy A. Bayoumi
    An Efficient Low-Bit Rate Motion Compensation Technique Based on Quadtree. [Citation Graph (0, 0)][DBLP]
    IEEE International Conference on Multimedia and Expo (I), 2000, pp:213-216 [Conf]
  28. Khaled M. Elleithy, Magdy A. Bayoumi
    Formal Synthesis of a Parallel Architectures from Recursive Equations. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:145-148 [Conf]
  29. Nam Ling, Magdy A. Bayoumi
    Algorithms for High Speed Multi-Dimensional Arithmetic and DSP Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:367-374 [Conf]
  30. Khaled M. Elleithy, Magdy A. Bayoumi
    From Algorithms to Parallel Architectures: A Formal Approach. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:358-363 [Conf]
  31. Qutaibah M. Malluhi, Magdy A. Bayoumi
    Properties and Performance of the Hierarchical Hypercube. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:47-50 [Conf]
  32. Qutaibah M. Malluhi, Magdy A. Bayoumi, T. R. N. Rao
    On the Hierarchical Hypercube Interconnection Network. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:524-530 [Conf]
  33. Majid M. Altuwaijri, Magdy A. Bayoumi
    Arabic Text Recognition Using Neural Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:415-418 [Conf]
  34. Majid M. Altowairjri, Magdy A. Bayoumi
    A New Thinning Algorithm for Arabic Character Using Self-Organizing Neural Network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1824-1827 [Conf]
  35. Ramy E. Aly, Mohamed A. Elgamel, Magdy A. Bayoumi
    Dual sense amplified bit lines (DSABL) architecture for low-power SRAM design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1650-1653 [Conf]
  36. Rafic A. Ayoubi, Haissam Ziade, Magdy A. Bayoumi
    Hopfield associative memory on mesh. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:800-803 [Conf]
  37. Archana Chidanandan, Magdy A. Bayoumi
    Enhanced Parallel Interference Cancellation using Decorrelator for the base-station receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:341-344 [Conf]
  38. Archana Chidanandan, Magdy A. Bayoumi
    Novel systolic array architecture for the decorrelator using conjugate gradient for least squares algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5437-5440 [Conf]
  39. Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi
    Noise-constrained interconnect optimization for nanometer technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:481-484 [Conf]
  40. H. Kumar, Magdy A. Bayoumi, Akhilesh Tyagi, Nam Ling, R. Kalyan
    Parallel Implementation of a Cut and Paste Maze Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2035-2038 [Conf]
  41. Ashok Kumar, J. Luis Tecpanecatl-Xihuitl, Magdy A. Bayoumi
    Low complexity decimation filter for multi-standard digital receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:552-555 [Conf]
  42. Yijun Li, Mahmoud Elassal, Magdy A. Bayoumi
    Power efficient architecture for (3, 6)-regular low-density parity-check code decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:81-84 [Conf]
  43. Yijun Li, Mohamed A. Elgamel, Magdy A. Bayoumi
    A partial parallel algorithm and architecture for arithmetic encoder in JPEG2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5198-5201 [Conf]
  44. N. A. Ramakrishna, Magdy A. Bayoumi
    Storage Allocation Strategies for Data Path Synthesis of ACICs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:41-44 [Conf]
  45. Wael M. Badawy, Magdy A. Bayoumi
    A mesh based motion tracking architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:262-265 [Conf]
  46. Ayman A. Fayed, Magdy A. Bayoumi
    A low power 10-transistor full adder cell for embedded architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:226-229 [Conf]
  47. Mohamed A. Elgamel, Ahmed M. Shams, Xi Xueling, Magdy A. Bayoumi
    Enhanced low power motion estimation VLSI architectures for video compression. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:474-477 [Conf]
  48. Ashok Kumar, Magdy A. Bayoumi
    Multiple voltage-based scheduling methodology for low power in the high level synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:371-374 [Conf]
  49. Ashok Kumar, Magdy A. Bayoumi, Raghava V. Cherabuddi
    Minimizing switchings of the function units through binding for low power. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:66-69 [Conf]
  50. Ahmed M. Shams, Magdy A. Bayoumi
    Performance evaluation of 1-bit CMOS adder cells. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:27-30 [Conf]
  51. Hanan A. Mahmoud, Magdy A. Bayoumi
    A 10-transistor low-power high-speed full adder cell. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:43-46 [Conf]
  52. Guoqing Zhang, M. Talley, Wael M. Badawy, Michael Weeks, Magdy A. Bayoumi
    A low power prototype for a 3D discrete wavelet transform processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:145-148 [Conf]
  53. Walid Elgharbawy, Magdy A. Bayoumi
    B-DTNMOS: a novel bulk dynamic threshold NMOS scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:413-416 [Conf]
  54. M. B. Maaz, Magdy A. Bayoumi
    A non-zero clock skew scheduling algorithm for high speed clock distribution network. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:382-385 [Conf]
  55. Ayman A. Fayed, Magdy A. Bayoumi
    Noise-tolerant design and analysis for a low-voltage dynamic full adder cell. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:579-582 [Conf]
  56. Charbel J. Akl, Magdy A. Bayoumi
    Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:219-224 [Conf]
  57. Mohamed A. Elgamel, Tarek Darwish, Magdy A. Bayoumi
    Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:89-94 [Conf]
  58. Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi
    Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:189-192 [Conf]
  59. Walid Elgharbawy, Magdy A. Bayoumi
    New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circui. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:115-120 [Conf]
  60. Sumeer Goel, Tarek Darwish, Magdy A. Bayoumi
    A Novel Technique for Noise-Tolerance in Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:203-206 [Conf]
  61. Ahmed M. Shams, Wendi Pan, Archana Chidanandan, Magdy A. Bayoumi
    A Low Power High Performance Distributed DCT Architecture. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:26-34 [Conf]
  62. Peiyi Zhao, Golconda Pradeep Kumar, C. Archana, Magdy A. Bayoumi
    A Double-Edge Implicit-Pulsed Level Convert Flip-Flop. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:141-144 [Conf]
  63. Mohamed A. Elgamel, Magdy A. Bayoumi
    On Low Power High Level Synthesis Using Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:37-40 [Conf]
  64. Chenyi Hu, Magdy A. Bayoumi, R. Baker Kearfott, Qing Yang
    A Parallelized Algorithm for the All-Row Preconditioned Interval Newton/Generalized Bisection Method. [Citation Graph (0, 0)][DBLP]
    PPSC, 1991, pp:205-209 [Conf]
  65. Mohamed A. Elgamel, Magdy A. Bayoumi
    Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:256-260 [Conf]
  66. Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi
    Novel Design Methodology for High-Performance XOR-XNOR Circuit Design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:71-0 [Conf]
  67. Qutaibah M. Malluhi, Magdy A. Bayoumi, T. R. N. Rao
    An Efficient Mapping of Multilayer Perceptron with Backpropagation ANNs on Hypercubes. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:368-375 [Conf]
  68. Hanan A. Mahmoud, Magdy A. Bayoumi
    Low-bit-rate generalized quad-tree motion compensation algorithm and its optimal encoding schemes. [Citation Graph (0, 0)][DBLP]
    VCIP, 2000, pp:230-237 [Conf]
  69. Hanan A. Mahmoud, Magdy A. Bayoumi
    Video codec incorporating block-based multihypothesis motion-compensated prediction. [Citation Graph (0, 0)][DBLP]
    VCIP, 2000, pp:238-251 [Conf]
  70. Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi
    Energy Efficient and Noise-Tolerant XOR-XNOR Circuit Design. [Citation Graph (0, 0)][DBLP]
    VLSI, 2003, pp:125-130 [Conf]
  71. Raghava V. Cherabuddi, Jijun Chen, Magdy A. Bayoumi
    A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:192-197 [Conf]
  72. M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi
    Parameterized Modeling of Open-Circuit Critical Volume for Three-Dimensional Defects in VLSI Processing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:333-338 [Conf]
  73. K. R. Rao, Magdy A. Bayoumi, T. V. Subramaniam
    T1: Multimedia. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:2-0 [Conf]
  74. Ashok Kumar, Magdy A. Bayoumi, Mohamed A. Elgamel
    A methodology for low power scheduling with resources operating at multiple voltages. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:37, n:1, pp:29-62 [Journal]
  75. Ashok Kumar, Magdy A. Bayoumi
    A Fast Scheduling Algorithm for Low Power Design. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:735-756 [Journal]
  76. Mohamed A. Elgamel, Magdy A. Bayoumi, Ahmed M. Shams, Bertrand Zavidovique
    Low Power Full Search Block Matching Motion Estimation Vlsi Architectures. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:6, pp:1271-1288 [Journal]
  77. Nam Ling, Magdy A. Bayoumi
    Systematic Algorithm Mapping for Multidimensional Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1989, v:7, n:2, pp:368-382 [Journal]
  78. Rafic A. Ayoubi, Qutaibah M. Malluhi, Magdy A. Bayoumi
    The Extended Cube Connected Cycles: An Efficient Interconnection for Massively Parallel Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:5, pp:609-614 [Journal]
  79. Qutaibah M. Malluhi, Magdy A. Bayoumi, T. R. N. Rao
    Correction to "Efficient Mapping of ANNs on Hypercube Massively Parallel Machines". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:511- [Journal]
  80. Qutaibah M. Malluhi, Magdy A. Bayoumi, T. R. N. Rao
    Efficient Mapping of ANNs on Hypercube Massively Parallel Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:6, pp:769-779 [Journal]
  81. M. K. Kidambi, Akhilesh Tyagi, Mohammed R. Madani, Magdy A. Bayoumi
    Three-dimensional defect sensitivity modeling for open circuits in ULSI structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:366-371 [Journal]
  82. Nam Ling, Magdy A. Bayoumi
    Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:8, pp:804-820 [Journal]
  83. Yijun Li, Magdy A. Bayoumi
    A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:9, pp:1153-1163 [Journal]
  84. Rafic A. Ayoubi, Magdy A. Bayoumi
    Efficient Mapping Algorithm of Multilayer Neural Network on Torus Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:9, pp:932-943 [Journal]
  85. Qutaibah M. Malluhi, Magdy A. Bayoumi
    The Hierarchical Hypercube: A New Interconnection Topology for Massively Parallel Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1994, v:5, n:1, pp:17-30 [Journal]
  86. Mohamed A. Elgamel, Ashok Kumar, Magdy A. Bayoumi
    Efficient shield insertion for inductive noise reduction in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:401-405 [Journal]
  87. Peiyi Zhao, Tarek Darwish, Magdy A. Bayoumi
    High-performance and low-power conditional discharge flip-flop. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:5, pp:477-484 [Journal]
  88. Sumeer Goel, Magdy A. Bayoumi
    Multi-Path Search Algorithm for Block-Based Motion Estimation. [Citation Graph (0, 0)][DBLP]
    ICIP, 2006, pp:2373-2376 [Conf]
  89. Peiyi Zhao, Jason McNeely, Magdy A. Bayoumi, Golconda Pradeep Kumar, Weidong Kuang
    A Low Power Domino with Differential-Controlled-Keeper. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1625-1628 [Conf]
  90. Abu Baker, Soumik Ghosh, Ashok Kumar, Magdy A. Bayoumi, Rafic A. Ayoubi
    Design and Realization of Analog Phi-Function for LDPC Decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1661-1664 [Conf]
  91. Yijun Li, M. Bayoumi
    A power-efficient architecture for EBCOT tier-1 in JPEG 2000. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  92. M. I. Faisal, Magdy A. Bayoumi, Peiyi Zhao
    A low-power clock frequency multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  93. Xiaodong Zhang, Magdy A. Bayoumi
    A low power adaptive transmitter architecture for low band UWB applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  94. Sumeer Goel, Ashok Kumar, Magdy A. Bayoumi
    Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1309-1321 [Journal]
  95. Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang
    Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:3, pp:338-345 [Journal]
  96. Ahmed M. Shams, T. K. Darwish, Magdy A. Bayoumi
    Performance analysis of low-power 1-bit CMOS full adder cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:20-29 [Journal]
  97. Ramy E. Aly, Magdy A. Bayoumi
    High-Speed and Low-Power IP for Embedded Block Coding with Optimized Truncation (EBCOT) Sub-Block in JPEG2000 System Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:2, pp:139-148 [Journal]
  98. Magdy A. Bayoumi, Nam Ling, Samia A. Mashali
    Editorial. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:42, n:1, pp:5-6 [Journal]

  99. Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects. [Citation Graph (, )][DBLP]


  100. Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count. [Citation Graph (, )][DBLP]


  101. Power analysis of the Huffman decoding tree. [Citation Graph (, )][DBLP]


  102. An efficient adaptive manipulation architecture for real time video coding in Frequency Domain. [Citation Graph (, )][DBLP]


  103. A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers. [Citation Graph (, )][DBLP]


  104. Cost-effective and low-power memory address bus encodings. [Citation Graph (, )][DBLP]


  105. A generalized fast motion estimation algorithm using external and internal stop search techniques for H.264 video coding standard. [Citation Graph (, )][DBLP]


  106. Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion. [Citation Graph (, )][DBLP]


  107. An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition. [Citation Graph (, )][DBLP]


  108. Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family. [Citation Graph (, )][DBLP]


  109. Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks. [Citation Graph (, )][DBLP]


  110. Self-Sleep Buffer for Distributed MTCMOS Design. [Citation Graph (, )][DBLP]


  111. Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling. [Citation Graph (, )][DBLP]


  112. Guaranteeing QoS with the pipelined multi-channel central caching NoC communication architecture. [Citation Graph (, )][DBLP]


  113. PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design. [Citation Graph (, )][DBLP]


  114. An Efficient Data Reuse Motion Estimation Engine. [Citation Graph (, )][DBLP]


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