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Publications of Author

1. George Broomell, J. Robert Heath
   An Integrated-Circuit Crossbar Switching System Design. [Citation Graph (0, 0)][DBLP]
   ICDCS, 1984, pp:278-287 [Conf]
   
2. J. Robert Heath, George Broomell, Andrew D. Hurt
   A distributed computer architecture for real-time, data driven applications. [Citation Graph (0, 0)][DBLP]
   ICDCS, 1982, pp:630-638 [Conf]
   
3. Andrew D. Hurt, J. Robert Heath
   The Design of a Fault-Tolerant Computing Element for Distributed Data Processors. [Citation Graph (0, 0)][DBLP]
   ICDCS, 1982, pp:171-176 [Conf]
   
4. J. Robert Heath, Andrew Tan
   Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2001, pp:128-135 [Conf]
   
5. J. Robert Heath, James Cline
   The Complexity and Use of a Multistage Interconnection Network for Distributed Processing Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Real-Time Systems Symposium, 1980, pp:28-35 [Conf]
   
6. Andrew D. Hurt, J. Robert Heath
   A Hardware Task Scheduling Mechanism for a Real-Time Multi-Microprocessor Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Real-Time Systems Symposium, 1982, pp:113-123 [Conf]
   
7. George Broomell, J. Robert Heath
   Classification Categories and Historical Development of Circuit Switching Topologies. [Citation Graph (0, 0)][DBLP]
   ACM Comput. Surv., 1983, v:15, n:2, pp:95-133 [Journal]
   
8. Tae Won Cho, Sam S. Pyo, J. Robert Heath
   PARALLEX: a parallel approach to switchbox routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:684-693 [Journal]
   
9. 
   Development and Validation of a Load Balancing and Control Mechanism for a Reconfigurable Single-Chip Heterogenous and Hybrid Multiprocessor Architecture Platform. [Citation Graph (, )][DBLP]
   
   
10. 
    A New Reconfigurable Network Node Processor Architecture for Distributed Implementation of Ephemeral State Processing. [Citation Graph (, )][DBLP]