The SCEAS System
Navigation Menu

Search the dblp DataBase


Ahmed Louri: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ahmed Louri
    A Symbolic Substitution Based Parallel Architecture and Algorithms for High-speed Parallel Processing. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer Science, 1990, pp:173-179 [Conf]
  2. Peng Yin Choo, Abram Detofsky, Ahmed Louri
    The Equivalency Processing Parallel Photonic Integrated Circuit (EP3IC), a Parallel Digital Equivalence Search Module. [Citation Graph (0, 0)][DBLP]
    AIPR, 2000, pp:64-70 [Conf]
  3. Earl Hokens, Ahmed Louri
    Performance Considerations Relating to the Design of Interconnection Networks for Multiprocessing Systems. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:206-209 [Conf]
  4. Kai Hwang, Ahmed Louri
    Optical Arithmetic Using Signed-Digit Symbolic Substitution. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:55-64 [Conf]
  5. Thomas S. Jones, Ahmed Louri
    Media Access Protocols For A Scalable Optical Interconnection Network. [Citation Graph (0, 0)][DBLP]
    ICPP, 1998, pp:304-0 [Conf]
  6. Sy-Yen Kuo, Ahmed Louri, Sheng-Chiech Liang
    Design and Evaluation of Fault-Tolerant Interleaved Memory Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:188-195 [Conf]
  7. Ahmed Louri, Hongki Sung
    A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:2-9 [Conf]
  8. Peng Yin Choo, Abram Detofsky, Ahmed Louri
    A Multi-Wavelength Optical Content-Addressable Parallel Processor (MW-OCAPP) for High-Speed Parallel Relational Database Processing: Architectural Concepts and Preliminary Experimental System. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1999, pp:873-886 [Conf]
  9. Avinash Karanth Kodi, Ahmed Louri
    A Scalable Architecture for Distributed Shared Memory Multiprocessors Using Optical Interconnects. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  10. Ahmed Louri
    Design of an Optical Content-Addressable Parallel Processor with Applications to Fast Searching and Information Retrieval. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:234-239 [Conf]
  11. Ahmed Louri, Kai Hwang
    A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:18-27 [Conf]
  12. Ahmed Louri
    An Optical Content-Adressable Parallel Processor for Fast Searching and Retrieving. [Citation Graph (0, 0)][DBLP]
    PARLE (1), 1991, pp:338-354 [Conf]
  13. Ahmed Louri, Kai Hwang
    A Parallel Architecture for Optical Computing. [Citation Graph (0, 0)][DBLP]
    PPSC, 1987, pp:414-418 [Conf]
  14. Ahmed Louri, James A. Hatch Jr.
    An Optical Associative Parallel Processor for High-Speed Database Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1994, v:27, n:11, pp:65-71 [Journal]
  15. Ahmed Louri, Hongki Sung
    3D Optical Interconnects for High-Speed Interchip and Interboard Communications. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1994, v:27, n:10, pp:27-37 [Journal]
  16. Bernard P. Zeigler, Ahmed Louri
    A Simulation Environment for Intelligent Machine Architectures. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:18, n:1, pp:77-88 [Journal]
  17. Avinash Karanth Kodi, Ahmed Louri
    Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:1, pp:41-49 [Journal]
  18. Ahmed Louri, Avinash Karanth Kodi
    An Optical Interconnection Network and a Modified Snooping Protocol for the Design of Large-Scale Symmetric Multiprocessors (SMPs). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:12, pp:1093-1104 [Journal]
  19. Ahmed Louri, Brent Weech, Costas Neocleous
    A Spanning Multichannel Linked Hypercube: A Gradually Scalable Optical Interconnection Network for Massively Parallel Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:5, pp:497-512 [Journal]
  20. Brian Webb, Ahmed Louri
    A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:5, pp:444-458 [Journal]
  21. Avinash Karanth Kodi, Ahmed Louri
    Power-Aware Bandwidth-Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-10 [Conf]

  22. Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures. [Citation Graph (, )][DBLP]

  23. A multilayer nanophotonic interconnection network for on-chip many-core communications. [Citation Graph (, )][DBLP]

  24. iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures. [Citation Graph (, )][DBLP]

  25. NBTI aware workload balancing in multi-core systems. [Citation Graph (, )][DBLP]

  26. Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs). [Citation Graph (, )][DBLP]

  27. Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems. [Citation Graph (, )][DBLP]

  28. Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. [Citation Graph (, )][DBLP]

  29. On-Chip photonic interconnects for scalable multi-core architectures. [Citation Graph (, )][DBLP]

Search in 0.004secs, Finished in 0.006secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002