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Ashwini K. Nanda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Ashwini K. Nanda, Hong Jiang
Analysis of Directory Based Cache Coherence Schemes with Multistage Networks. [Citation Graph (0, 0)][DBLP]
ACM Conference on Computer Science, 1992, pp:485-492 [Conf] - Ashwini K. Nanda, Kwok-Ken Mak, Krishnan Sugavanam, Ramendra K. Sahoo, Vijayaraghavan Soundararajan, T. Basil Smith
MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design. [Citation Graph (0, 0)][DBLP]
ASPLOS, 2000, pp:37-48 [Conf] - Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas
Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. [Citation Graph (0, 0)][DBLP]
HPCA, 1999, pp:322- [Conf] - Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph
High-Throughput Coherence Controllers. [Citation Graph (0, 0)][DBLP]
HPCA, 2000, pp:145-155 [Conf] - Maged M. Michael, Ashwini K. Nanda
Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
HPCA, 1999, pp:142-151 [Conf] - Ashwini K. Nanda, Doug DeGroot, Daniel L. Stenger
Scheduling Directed Task Graphs on Multiprocessors Using Simulated Annealing. [Citation Graph (0, 0)][DBLP]
ICDCS, 1992, pp:20-27 [Conf] - Laxmi N. Bhuyan, Ashwini K. Nanda, Tahsin Askar
Performance and Reliability of the Multistage Bus Network. [Citation Graph (0, 0)][DBLP]
ICPP (1), 1994, pp:26-33 [Conf] - Ashwini K. Nanda, Laxmi N. Bhuyan
A Formal Specification and Verification Technique for Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
ICPP (1), 1992, pp:22-26 [Conf] - Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
IPDPS, 2000, pp:721-728 [Conf] - Ashwini K. Nanda, Yiming Hu, Moriyoshi Ohara, Caroline Benveniste, Mark Giampapa, Maged M. Michael
The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
IPPS/SPDP, 1998, pp:503-509 [Conf] - Anthony-Trung Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini K. Nanda, Maged M. Michael
Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation. [Citation Graph (0, 0)][DBLP]
IPPS, 1997, pp:39-44 [Conf] - Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim, Michael L. Scott
Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
ISCA, 1997, pp:219-228 [Conf] - Uming Ko, Poras T. Balsara, Ashwini K. Nanda
Energy optimization of multi-level processor cache architectures. [Citation Graph (0, 0)][DBLP]
ISLPD, 1995, pp:45-49 [Conf] - James O. Bondi, Ashwini K. Nanda, Simonjit Dutta
Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. [Citation Graph (0, 0)][DBLP]
MICRO, 1996, pp:14-23 [Conf] - Ashwini K. Nanda, Laxmi N. Bhuyan
Mapping Applications onto a Cache Coherent Multiprocessor. [Citation Graph (0, 0)][DBLP]
SC, 1992, pp:368-377 [Conf] - Kimberly Keeton, Russell M. Clapp, Ashwini K. Nanda
Guest Editors' Introduction: Evaluating Servers with Commercial Workloads. [Citation Graph (0, 0)][DBLP]
IEEE Computer, 2003, v:36, n:2, pp:29-32 [Journal] - Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph
High-throughout coherence control and hardware messaging in Everest. [Citation Graph (0, 0)][DBLP]
IBM Journal of Research and Development, 2001, v:45, n:2, pp:229-244 [Journal] - Bruce D'Amora, Ashwini K. Nanda, Karen A. Magerlein, Atman Binstock, Bernard Yee
High-performance server systems and the next generation of online games. [Citation Graph (0, 0)][DBLP]
IBM Systems Journal, 2006, v:45, n:1, pp:103-118 [Journal] - Ashwini K. Nanda, James O. Bondi, Simonjit Dutta
The Misprediction Recovery Cache. [Citation Graph (0, 0)][DBLP]
International Journal of Parallel Programming, 1998, v:26, n:4, pp:383-415 [Journal] - Ashwini K. Nanda, Laxmi N. Bhuyan
Efficient Mapping of Applications on Cache Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
J. Parallel Distrib. Comput., 1993, v:19, n:3, pp:179-191 [Journal] - Michel Dubois, Jaeheon Jeong, Ashwini K. Nanda
Shared cache architectures for decision support systems. [Citation Graph (0, 0)][DBLP]
Perform. Eval., 2002, v:49, n:1/4, pp:283-298 [Journal] - Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim
Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1999, v:48, n:2, pp:245-255 [Journal] - Ashwini K. Nanda, Laxmi N. Bhuyan
Design and Analysis of Cache Coherent Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1993, v:42, n:4, pp:458-470 [Journal] - Laxmi N. Bhuyan, Ravi R. Iyer, Tahsin Askar, Ashwini K. Nanda, Mohan Kumar
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:1, pp:82-95 [Journal] - Yiming Hu, Ashwini K. Nanda, Qing Yang
Measurement, analysis and performance improvement of the Apache Web server. [Citation Graph (0, 0)][DBLP]
IPCCC, 1999, pp:261-267 [Conf] - Uming Ko, Poras T. Balsara, Ashwini K. Nanda
Energy optimization of multilevel cache architectures for RISC and CISC processors. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:299-308 [Journal]
Multistage bus network (MBN): an interconnection network for cache coherent multiprocessors. [Citation Graph (, )][DBLP]
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