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Christos A. Papachristou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Christos A. Papachristou
    Expert system approach to VLSI cell design (abstract). [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer Science, 1986, pp:485- [Conf]
  2. Kowen Lai, Christos A. Papachristou
    BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:219-0 [Conf]
  3. Kowen Lai, Christos A. Papachristou, Mikhail Baklashov
    BIST testability enhancement using high level test synthesis for behavioral and structural designs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:338-342 [Conf]
  4. Francis G. Wolff, Michael J. Knieser, Daniel J. Weyer, Christos A. Papachristou
    Using codesign techniques to support analog functionality. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:79-84 [Conf]
  5. Scott Chiu, Christos A. Papachristou
    A Design for Testability Scheme with Applications to Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:271-277 [Conf]
  6. Ehat Ercanli, Christos A. Papachristou
    A Register File and Scheduling Model for Application Specific Processor Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:35-40 [Conf]
  7. Wen-Ben Jone, Christos A. Papachristou
    A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:525-534 [Conf]
  8. Wen-Ben Jone, Christos A. Papachristou, M. Pereira
    A Scheme for Overlaying Concurrent Testing of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:531-536 [Conf]
  9. Mehrdad Nourani, Joan Carletta, Christos A. Papachristou
    Synthesis-for-testability of controller-datapath pairs that use gated clocks. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:613-618 [Conf]
  10. Mehrdad Nourani, Joan Carletta, Christos A. Papachristou
    A Scheme for Integrated Controller-Datapath Fault Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:546-551 [Conf]
  11. Mehrdad Nourani, Christos A. Papachristou
    Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:99-105 [Conf]
  12. Mehrdad Nourani, Christos A. Papachristou
    A Layout Estimation Algorithm for RTL Datapaths. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:285-291 [Conf]
  13. Kelly A. Ockunzzi, Christos A. Papachristou
    Test Strategies for BIST at the Algorithmic and Register-Transfer Levels. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:65-70 [Conf]
  14. Christos A. Papachristou, Scott Chiu, Haidar Harmanani
    A Data Path Synthesis Method for Self-Testable Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:378-384 [Conf]
  15. Christos A. Papachristou, Haidar Harmanani, Mehrdad Nourani
    An Approach for Redesigning in Data Path Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:419-423 [Conf]
  16. Christos A. Papachristou, Haluk Konuk
    A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:77-83 [Conf]
  17. Christos A. Papachristou, F. Martin, Mehrdad Nourani
    Microprocessor Based Testing for Core-Based System on Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:586-591 [Conf]
  18. Christos A. Papachristou, Mark Spining, Mehrdad Nourani
    An Effective Power Management Scheme for RTL Design Based on Multiple Clocks. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:337-342 [Conf]
  19. Shih-yu Yang, Christos A. Papachristou, Massood Tabib-Azar
    Improving Bus Test Via IDDT and Boundary Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:307-312 [Conf]
  20. Joan Carletta, Mehrdad Nourani, Christos A. Papachristou
    Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:278-282 [Conf]
  21. Joan Carletta, Christos A. Papachristou, Mehrdad Nourani
    Detecting Undetectable Controller Faults Using Power Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:723-728 [Conf]
  22. Balkaran S. Gill, Michael Nicolaidis, Francis G. Wolff, Christos A. Papachristou, Steven L. Garverick
    An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:592-597 [Conf]
  23. Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff
    Soft delay error analysis in logic circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:47-52 [Conf]
  24. Michael J. Knieser, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, David R. McIntyre
    A Technique for High Ratio LZW Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10116-10121 [Conf]
  25. Mehrdad Nourani, Christos A. Papachristou
    A Bypass Scheme for Core-Based System Fault Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:979-980 [Conf]
  26. Christos A. Papachristou, Yusuf Alzazeri
    A Method of Distributed Controller Design for RTL Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:774-775 [Conf]
  27. Hani Rizk, Christos A. Papachristou, Francis G. Wolff
    Designing Self Test Programs for Embedded DSP Cores. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:816-823 [Conf]
  28. Francis G. Wolff, Christos A. Papachristou, David R. McIntyre
    Test Compression and Hardware Decompression for Scan-Based SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:716-717 [Conf]
  29. Wei Zhao, Christos A. Papachristou
    Testing DSP Cores Based on Self-Test Programs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:166-172 [Conf]
  30. Jianchun Li, Christos A. Papachristou, Raj Shekhar
    A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:320-321 [Conf]
  31. Jianchun Li, Christos A. Papachristou, Raj Shekhar
    Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:279- [Conf]
  32. Haidar Harmanani, Christos A. Papachristou
    An improved method for RTL synthesis with testability tradeoffs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:30-35 [Conf]
  33. Christos A. Papachristou, Mikhail Baklashov
    A test synthesis technique using redundant register transfers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:414-420 [Conf]
  34. Wei Zhao, Christos A. Papachristou
    Architectural partitioning of control memory for application specific programmable processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:521-526 [Conf]
  35. Wei Zhao, Christos A. Papachristou
    Synthesis of reusable DSP cores based on multiple behaviors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:103-108 [Conf]
  36. Joan Carletta, Christos A. Papachristou
    Testability analysis and insertion for RTL circuits based on pseudorandom BIST. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:162-167 [Conf]
  37. Scott Chiu, Christos A. Papachristou
    A Built-In Self-Testing Approach for Minimizing Hardware Overhead. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:282-285 [Conf]
  38. Scott Chiu, Christos A. Papachristou
    A Partial Scan Cost Estimation Method at the System Level. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:146-150 [Conf]
  39. Kowen Lai, Christos A. Papachristou, Mikhail Baklashov
    High Level Test Synthesis Across the Boundary of Behavioral and Structural Domains. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:636-641 [Conf]
  40. Christos A. Papachristou, Scott Chiu, Haidar Harmanani
    SYNTEST: A Method for High-Level SYNthesis with Self-TESTability. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:458-462 [Conf]
  41. H. Fatih Ugurdag, Christos A. Papachristou
    ALMP: A Shifting Memory Architecture for Loop Pipelining. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:564-568 [Conf]
  42. Christos A. Papachristou, Suntae Hwang
    A Systolic Array Structure for Matrix Multiplication in the Residue Number System. [Citation Graph (0, 0)][DBLP]
    ICS, 1987, pp:716-731 [Conf]
  43. Balkaran S. Gill, Michael Nicolaidis, Christos A. Papachristou
    Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:266-271 [Conf]
  44. Jianchun Li, Christos A. Papachristou, Raj Shekhar
    A "Brick" Caching Scheme for 3D Medical Imaging. [Citation Graph (0, 0)][DBLP]
    ISBI, 2004, pp:563-566 [Conf]
  45. Christos A. Papachristou, Mark Spining, Mehrdad Nourani
    A multiple clocking scheme for low power RTL design. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:27-32 [Conf]
  46. Mehrdad Nourani, Christos A. Papachristou
    An ILP formulation to optimize test access mechanism in system-on-chip testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:902-910 [Conf]
  47. Kelly A. Ockunzzi, Christos A. Papachristou
    Testability Enhancement for Behavioral Descriptions Containing Conditional Statements. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:236-245 [Conf]
  48. Christos A. Papachristou
    High Time for Higher Level BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1117- [Conf]
  49. Christos A. Papachristou, Joan Carletta
    Test Synthesis in the Behavioral Domain. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:693-702 [Conf]
  50. Francis G. Wolff, Christos A. Papachristou
    Multiscan-Based Test Compression and Hardware Decompression Using LZ77. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:331-339 [Conf]
  51. Michael J. Knieser, Christos A. Papachristou
    Y-Pipe: a conditional branching scheme without pipeline delays. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:125-128 [Conf]
  52. Jong-Jiann Shieh, Christos A. Papachristou
    On reordering instruction streams for pipelined computers. [Citation Graph (0, 0)][DBLP]
    MICRO, 1989, pp:199-206 [Conf]
  53. Jong-Jiann Shieh, Christos A. Papachristou
    An instruction reoderer for pipelined computers. [Citation Graph (0, 0)][DBLP]
    MICRO, 1990, pp:135-142 [Conf]
  54. L. Shih, Christos A. Papachristou
    Mapping of micro data flow computations on parallel microarchitectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:70-72 [Conf]
  55. Djahida Smati, Jerry Hwang, Christos A. Papachristou
    SMDSS - a structured microcode development and simulation system. [Citation Graph (0, 0)][DBLP]
    MICRO, 1990, pp:252-259 [Conf]
  56. H. Fatih Ugurdag, Christos A. Papachristou
    A VLIW architecture based on shifting register files. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:263-268 [Conf]
  57. Joan Carletta, Christos A. Papachristou
    Structural constraints for circular self-test paths. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:486-491 [Conf]
  58. Ken Batcher, Christos A. Papachristou
    Instruction Randomization Self Test For Processor Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:34-40 [Conf]
  59. J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard
    Hardware-Software Co-Design for Test: It's the Last Straw! [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:506-507 [Conf]
  60. Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff
    Soft Delay Error Effects in CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:325-334 [Conf]
  61. Kelly A. Ockunzzi, Christos A. Papachristou
    Breaking Correlation to Improve Testability. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:75-81 [Conf]
  62. Mehrdad Nourani, Christos A. Papachristou
    Parallelism in Structural Fault Testing of Embedded Cores. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:15-21 [Conf]
  63. Gorn Tepvorachai, Christos A. Papachristou
    Self-Configurable Neural Network Processor for FIR Filter Applications. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:114-121 [Conf]
  64. Osama Al-Khaleel, Christos A. Papachristou, Frank Wolff, Kiamal Z. Pekmestzi
    A Large Scale Adaptable Multiplier for Cryptographic Applications. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:477-484 [Conf]
  65. Christos A. Papachristou
    Characteristic measures of switching functions. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1977, v:13, n:1, pp:51-75 [Journal]
  66. Christos A. Papachristou
    Associative table lookup processing for multioperand residue arithmetic. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1987, v:34, n:2, pp:376-396 [Journal]
  67. Christos A. Papachristou
    An Algorithm for Optimal NAND Cascade Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:12, pp:1099-1111 [Journal]
  68. Christos A. Papachristou
    Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:10, pp:961-968 [Journal]
  69. Christos A. Papachristou, Venkata R. Immaneni
    Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:1, pp:45-61 [Journal]
  70. Christos A. Papachristou, Narendar B. Sahgal
    An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:2, pp:110-116 [Journal]
  71. Wen-Ben Jone, Christos A. Papachristou
    A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:374-384 [Journal]
  72. Christos A. Papachristou, Anil L. Pandya
    A design scheme for PLA-based control tables with reduced area and time-delay cost. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:453-472 [Journal]
  73. Shih-yu Yang, Christos A. Papachristou
    A method for detecting interconnect DSM defects in systems on chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:197-204 [Journal]
  74. Mehrdad Nourani, Joan Carletta, Christos A. Papachristou
    Integrated test of interacting controllers and datapaths. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:3, pp:401-422 [Journal]
  75. Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff
    Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1460-1465 [Conf]
  76. Christos A. Papachristou, J. Weaver, R. Vijayakumar, Francis G. Wolff
    A Dynamic Reconfigurable Fabric for Platform SoCs. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  77. Osama Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi
    An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:71-78 [Conf]
  78. Christos A. Papachristou, Mehrdad Nourani, Mark Spining
    A multiple clocking scheme for low-power RTL design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:266-276 [Journal]
  79. Mehrdad Nourani, Christos A. Papachristou
    Stability-based algorithms for high-level synthesis of digital ASICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:431-435 [Journal]
  80. Mehrdad Nourani, Christos A. Papachristou
    False path exclusion in delay analysis of RTL structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:30-43 [Journal]
  81. Hani Rizk, Christos A. Papachristou, Francis G. Wolff
    A Self Test Program Design Technique for Embedded DSP Cores. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:1, pp:71-87 [Journal]

  82. MERO: A Statistical Approach for Hardware Trojan Detection. [Citation Graph (, )][DBLP]


  83. Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. [Citation Graph (, )][DBLP]


  84. Structural BIST insertion using behavioral test analysis. [Citation Graph (, )][DBLP]


  85. A high-speed radix-4 multiplexer-based array multiplier. [Citation Graph (, )][DBLP]


  86. FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems. [Citation Graph (, )][DBLP]


  87. Multi-label imbalanced data enrichment process in neural net classifier training. [Citation Graph (, )][DBLP]


  88. SRAM Cell Design Protected from SEU Upsets. [Citation Graph (, )][DBLP]


  89. SRAM cell design using tri-state devices for SEU protection. [Citation Graph (, )][DBLP]


  90. A Configurable FIR Filter Scheme based on an Adaptive Multilayer Network Structure. [Citation Graph (, )][DBLP]


  91. Facial Image Associative Memory Model. [Citation Graph (, )][DBLP]


  92. Avoiding Delay Jitter in Cyber-Physical Systems Using One Way Delay Variations Model. [Citation Graph (, )][DBLP]


  93. An Embedded Flash Memory Vault for Software Trojan Protection. [Citation Graph (, )][DBLP]


  94. Dynamic Evaluation of Hardware Trust. [Citation Graph (, )][DBLP]


  95. An Improved Algorithm to Smooth Delay Jitter in Cyber-Physical Systems. [Citation Graph (, )][DBLP]


  96. Hardware Trojan by Hot Carrier Injection [Citation Graph (, )][DBLP]


  97. Exploiting Semiconductor Properties for Hardware Trojans [Citation Graph (, )][DBLP]


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