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Publications of Author

1. William A. Rogers, Jacob A. Abraham
   High level hierarchical fault simulation techniques. [Citation Graph (0, 0)][DBLP]
   ACM Conference on Computer Science, 1985, pp:89-97 [Conf]
   
2. Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers
   Fault Simulation in a Distributed Environment. [Citation Graph (0, 0)][DBLP]
   DAC, 1988, pp:686-691 [Conf]
   
3. Mark D. Sloan, William A. Rogers, Srihari Shoroff
   The Impedance Fault Model and Design for Robust Impedance Fault Testability. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1991, pp:504-507 [Conf]
   
4. Sanghyeon Baeg, William A. Rogers
   A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits. [Citation Graph (0, 0)][DBLP]
   ICCD, 1994, pp:354-358 [Conf]
   
5. Mark A. Heap, William A. Rogers, M. Ray Mercer
   A Synthesis Algorithm for Two-Level XOR Based Circuits. [Citation Graph (0, 0)][DBLP]
   ICCD, 1992, pp:459-463 [Conf]
   
6. Sanghyeon Baeg, William A. Rogers
   Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation. [Citation Graph (0, 0)][DBLP]
   ITC, 1994, pp:340-349 [Conf]
   
7. Hongtao P. Chang, William A. Rogers, Jacob A. Abraham
   Structured Functional Level Test Generation Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
   ITC, 1986, pp:97-104 [Conf]
   
8. Hyoung B. Min, William A. Rogers
   Search Strategy Switching: An Alternative to Increased Backtracking. [Citation Graph (0, 0)][DBLP]
   ITC, 1989, pp:803-811 [Conf]
   
9. William A. Rogers, Jacob A. Abraham
   CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator. [Citation Graph (0, 0)][DBLP]
   ITC, 1985, pp:710-716 [Conf]
   
10. Mark A. Heap, William A. Rogers
    Generating Single-Sstuck-Fault Coverage from a Collapsed-Fault Set. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:4, pp:51-57 [Journal]
    
11. Sanghyeon Baeg, William A. Rogers
    A cost-effective design for testability: clock line control and test generation using selective clocking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:850-861 [Journal]
    
12. Hyoung B. Min, Hwei-Tsu Ann Luh, William A. Rogers
    Hierarchical test pattern generation: a cost model and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1029-1039 [Journal]
    
13. William A. Rogers, John F. Guzolek, Jacob A. Abraham
    Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:848-862 [Journal]