The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Jacob A. Abraham: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ghani A. Kanawati, Nasser A. Kanawati, Jacob A. Abraham
    FERRARI: A Flexible Software-Based Fault and Error Injection System. [Citation Graph (2, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:2, pp:248-260 [Journal]
  2. Prithviraj Banerjee, Jacob A. Abraham
    Fault-Secure Algorithms for Multiple-Processor Systems. [Citation Graph (1, 0)][DBLP]
    ISCA, 1984, pp:279-287 [Conf]
  3. Timothy C. K. Chou, Jacob A. Abraham
    Load Balancing in Distributed Systems. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Software Eng., 1982, v:8, n:4, pp:401-412 [Journal]
  4. William A. Rogers, Jacob A. Abraham
    High level hierarchical fault simulation techniques. [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer Science, 1985, pp:89-97 [Conf]
  5. Qingqi Dou, Jacob A. Abraham
    Jitter decomposition in ring oscillators. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:285-290 [Conf]
  6. Jianhua Gan, Shouli Yan, Jacob A. Abraham
    Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:292-297 [Conf]
  7. Nina Saxena, Jacob A. Abraham, Avijit Saha
    Causality based generation of directed test cases. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:503-508 [Conf]
  8. Hak-soo Yu, Jacob A. Abraham
    An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:441-446 [Conf]
  9. Jason Baumgartner, Andreas Kuehlmann, Jacob A. Abraham
    Property Checking via Structural Analysis. [Citation Graph (0, 0)][DBLP]
    CAV, 2002, pp:151-165 [Conf]
  10. Jun Yuan, Jian Shen, Jacob A. Abraham, Adnan Aziz
    On Combining Formal and Informal Verification. [Citation Graph (0, 0)][DBLP]
    CAV, 1997, pp:376-387 [Conf]
  11. Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir
    Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:386-402 [Conf]
  12. Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther
    Microprocessor Testing: Which Technique is Best? (Panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:294- [Conf]
  13. David Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh
    Automatic Generation of Behavioral Models from Switch-Level Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:179-184 [Conf]
  14. Hoon Chang, Jacob A. Abraham
    VIPER: An Efficient Vigorously Sensitizable Path Extractor. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:112-117 [Conf]
  15. Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers
    Fault Simulation in a Distributed Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:686-691 [Conf]
  16. Gopi Ganapathy, Jacob A. Abraham
    Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:550-555 [Conf]
  17. Carol V. Gura, Jacob A. Abraham
    Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:300-305 [Conf]
  18. Carol V. Gura, Jacob A. Abraham
    Average Interconnection Length and Interconnection Distribution Based on Rent's Rule. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:574-577 [Conf]
  19. Ramachandra P. Kunda, Jacob A. Abraham, Bharat Deep Rathi, Prakash Narain
    Speed Up of Test Generation Using High-Level Primitives. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:594-599 [Conf]
  20. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    DRAFTS: Discretized Analog Circuit Fault Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:509-514 [Conf]
  21. Richard Raimi, Jacob A. Abraham
    Detecting False Timing Paths: Experiments on PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:737-741 [Conf]
  22. Kaushik Roy, Jacob A. Abraham
    A Novel Approach to Accurate Timing Verification Using RTL Descriptions. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:638-641 [Conf]
  23. Jian Shen, Jacob A. Abraham, Dave Baker, Tony Hurson, Martin Kinkade, Gregorio Gervasio, Chen-chau Chu, Guanghui Hu
    Functional Verification of the Equator MAP1000 Microprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:169-174 [Conf]
  24. Hsi-Ching Shih, Jacob A. Abraham
    Transistor-level test generation for physical failures in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:243-249 [Conf]
  25. Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham
    Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:647-652 [Conf]
  26. Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir
    Automatic Test Knowledge Extraction from VHDL (ATKET). [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:273-278 [Conf]
  27. Jing Zeng, Magdy S. Abadir, Jacob A. Abraham
    False timing path identification using ATPG techniques and delay-based information. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:562-565 [Conf]
  28. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
    An Efficient Filter-Based Approach for Combinational Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:132-137 [Conf]
  29. Vivekananda M. Vedula, Jacob A. Abraham
    FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:730-735 [Conf]
  30. Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.
    Automatic insertion of low power annotations in RTL for pipelined microprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:496-501 [Conf]
  31. Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham
    Full chip false timing path identification: applications to the PowerPCTM microprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:514-519 [Conf]
  32. Jacob A. Abraham, Arun Krishnamachary, Raghuram S. Tupuri
    A Comprehensive Fault Model for Deep Submicron Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:360-364 [Conf]
  33. Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.
    Quadruple Time Redundancy Adders. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:250-256 [Conf]
  34. Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka
    Adaptive Design for Performance-Optimized Robustness. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:3-11 [Conf]
  35. Jacob A. Abraham
    Research in Reliable VLSI Architectures at the University of Illinois. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:890-893 [Conf]
  36. Chien-Yi Chen, Jacob A. Abraham
    On the Design of Fault-Tolerant Systolic Arrays with Linear Cells. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:400-409 [Conf]
  37. Kien A. Hua, Jacob A. Abraham
    Design of Systems with Concurrent Error Detection Using Software Redundancy. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:826-835 [Conf]
  38. Qiang Qiang, Daniel G. Saab, Jacob A. Abraham
    An Emulation Model for Sequential ATPG-Based Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:469-474 [Conf]
  39. Daniel G. Saab, Fatih Kocan, Jacob A. Abraham
    Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1172-1176 [Conf]
  40. James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
    Efficient Algorithmic Circuit Verification Using Indexed BDDs. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:266-275 [Conf]
  41. Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell
    From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel). [Citation Graph (0, 0)][DBLP]
    FTCS, 1998, pp:296-301 [Conf]
  42. Junsheng Long, W. Kent Fuchs, Jacob A. Abraham
    Compiler-Assisted Static Checkpoint Insertion. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:58-65 [Conf]
  43. Ghani A. Kanawati, Nasser A. Kanawati, Jacob A. Abraham
    FERRARI: A Tool for The Validation of System Dependability Properties. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:336-344 [Conf]
  44. Praveen Vishakantaiah, Jacob A. Abraham
    Impact of Behavioral Learning on the Compilation of Sequential Circuit Tests. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:370-379 [Conf]
  45. Prakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu
    A Hierarchal Approach for Power Reduction in VLSI Chips. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:182-0 [Conf]
  46. Ji Hwan (Paul) Chun, Hak-soo Yu, Jacob A. Abraham
    An efficient linearity test for on-chip high speed ADC and DAC using loop-back. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:328-331 [Conf]
  47. Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham
    On-chip delay measurement for silicon debug. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:145-148 [Conf]
  48. Jianhua Gan, Shouli Yan, Jacob A. Abraham
    Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:161-164 [Conf]
  49. Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell
    Automated verification of temporal properties specified as state machines in VHDL. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:100-105 [Conf]
  50. Sungbae Hwang, Jacob A. Abraham
    Selective-run built-in self-test using an embedded processor. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:124-129 [Conf]
  51. Chia-Pin R. Liu, Jacob A. Abraham
    Transistor Level Synthesis for Static CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:172-175 [Conf]
  52. Arun Krishnamachary, Jacob A. Abraham
    Test generation for resistive opens in CMOS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:65-70 [Conf]
  53. Dinos Moundanos, Jacob A. Abraham
    Formal Checking of Properties in Complex Systems Using Abstractions. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:280-283 [Conf]
  54. Hongjoong Shin, Hak-soo Yu, Jacob A. Abraham
    LFSR-based BIST for analog circuits using slope detection. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:316-321 [Conf]
  55. Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham
    Reducing verification overhead with RTL slicing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:399-404 [Conf]
  56. Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob Abraham
    Estimating path delay distribution considering coupling noise. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:61-66 [Conf]
  57. Robert W. Sumners, Jacob A. Abraham
    Hierarchical Specification of System Behavior. [Citation Graph (0, 0)][DBLP]
    HASE, 1997, pp:134-140 [Conf]
  58. David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham
    SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:66-69 [Conf]
  59. Chun-Hung Chen, Jacob A. Abraham
    Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:230-233 [Conf]
  60. Abhijit Chatterjee, Jacob A. Abraham
    RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:340-343 [Conf]
  61. Sujit Dey, Jacob A. Abraham, Yervant Zorian
    High-level design validation and test. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:3- [Conf]
  62. Jawahar Jain, Jim Bitner, Donald S. Fussell, Jacob A. Abraham
    Probabilistic Design Verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:468-471 [Conf]
  63. Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
    Fault-based automatic test generator for linear analog circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:88-91 [Conf]
  64. Jeongjin Roh, Suresh Seshadri, Jacob A. Abraham
    Verification of Delta-Sigma Converters Using Adaptive Regression Modeling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:182-187 [Conf]
  65. Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu
    Automatic test generation for linear digital systems with bi-level search using matrix transform methods. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:224-228 [Conf]
  66. Daniel G. Saab, Youssef Saab, Jacob A. Abraham
    CRIS: a test cultivation program for sequential VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:216-219 [Conf]
  67. Daniel G. Saab, Youssef Saab, Jacob A. Abraham
    Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:40-43 [Conf]
  68. Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham
    A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:302-305 [Conf]
  69. Yatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham
    Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:532-537 [Conf]
  70. Sankaran Karthik, Jacob A. Abraham
    Distributed VLSI Simulation on a Network of Workstations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:508-511 [Conf]
  71. Sankaran Karthik, Indira de Souza, Joseph T. Rahmeh, Jacob A. Abraham
    Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:393-396 [Conf]
  72. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    MIXER: Mixed-Signal Fault Simulator. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:568-571 [Conf]
  73. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    A Signature Analyzer for Analog and Mixed-signal Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:284-287 [Conf]
  74. Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham
    Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:461-463 [Conf]
  75. Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham
    Improving Witness Search Using Orders on States. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:452-457 [Conf]
  76. S. Surya, Pradip Bose, Jacob A. Abraham
    Architectural Performance Verification: PowerPCTM Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:344-347 [Conf]
  77. Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir
    AMBIANT: Automatic Generation of Behavioral Modifications for Testability. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:63-66 [Conf]
  78. Hak-soo Yu, Songjun Lee, Jacob A. Abraham
    An Adder Using Charge Sharing and its Application in DRAMs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:311-317 [Conf]
  79. Jing-Yang Jou, Jacob A. Abraham
    Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:359-362 [Conf]
  80. Junsheng Long, W. Kent Fuchs, Jacob A. Abraham
    Forward Recovery Using Checkpointing in Parallel Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:272-275 [Conf]
  81. Jacob A. Abraham
    Advances in VLSI-Testing. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:1013-1018 [Conf]
  82. Shobha Vasudevan, Jacob A. Abraham
    Static program transformations for efficient software model checking. [Citation Graph (0, 0)][DBLP]
    IFIP Congress Topical Sessions, 2004, pp:257-282 [Conf]
  83. Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala
    On-Line Error Detecting Constant Delay Adder. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:17-0 [Conf]
  84. Ramtilak Vemu, Jacob A. Abraham
    CEDA: Control-flow Error Detection through Assertions. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:151-158 [Conf]
  85. W. Kent Fuchs, Jacob A. Abraham, Kuang-Hua Huang
    Concurrent Error Detection in VLSI Interconnection Networks [Citation Graph (0, 0)][DBLP]
    ISCA, 1983, pp:309-315 [Conf]
  86. Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham
    TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:28-35 [Conf]
  87. Richard L. Norton, Jacob A. Abraham
    Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets [Citation Graph (0, 0)][DBLP]
    ISCA, 1983, pp:277-282 [Conf]
  88. Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka
    A low latency and low power dynamic Carry Save Adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:477-480 [Conf]
  89. Qingqi Dou, Jacob A. Abraham
    Jitter Decomposition by Time Lag Correlation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:525-530 [Conf]
  90. Kamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham
    Native Mode Functional Self-Test Generation for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:280-285 [Conf]
  91. Rajeshwary Tayade, Savithri Sundereswaran, Jacob Abraham
    Small-Delay Defect Detection in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:711-716 [Conf]
  92. Joonsung Park, Hongjoong Shin, Jacob A. Abraham
    Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:495-500 [Conf]
  93. Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham
    Built-In Test of RF Mixers Using RF Amplitude Detectors. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:404-409 [Conf]
  94. Jacob A. Abraham
    Functional Level Test Generation for Complex Digital Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1981, pp:461-462 [Conf]
  95. Jacob A. Abraham
    Incorporating Test Technology into an Undergraduate Curriculum. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:162- [Conf]
  96. Jacob A. Abraham
    Position Statement: Increasing Test Coverage in a VLSI Design Course. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1132- [Conf]
  97. Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab
    Verifying Properties Using Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:194-202 [Conf]
  98. Prithviraj Banerjee, Jacob A. Abraham
    Generating Tests for Physical Failures in MOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:554-559 [Conf]
  99. Kyung Tek Lee, Jacob A. Abraham
    Critical path identification and delay tests of dynamic circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:421-430 [Conf]
  100. Hongtao P. Chang, William A. Rogers, Jacob A. Abraham
    Structured Functional Level Test Generation Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:97-104 [Conf]
  101. Chun-Hung Chen, Jacob A. Abraham
    High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:615-622 [Conf]
  102. Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham
    Design of Test Pattern Generators for Built-In Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:315-319 [Conf]
  103. Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu
    Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1118-1127 [Conf]
  104. Robert H. Fujii, Jacob A. Abraham
    Self-Test for Microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:356-361 [Conf]
  105. Robert H. Fujii, Jacob A. Abraham
    Approaches to Circuit Level Design for Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:480-483 [Conf]
  106. Gopi Ganapathy, Jacob A. Abraham
    Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:848-857 [Conf]
  107. Sungbae Hwang, Jacob A. Abraham
    Optimal BIST Using an Embedded Microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:736-745 [Conf]
  108. Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham
    Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:160-166 [Conf]
  109. Marc E. Levitt, Jacob A. Abraham
    The Economics of Scan Design. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:869-874 [Conf]
  110. M. J. Marlett, Jacob A. Abraham
    DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:839-844 [Conf]
  111. John Moondanos, Jacob A. Abraham
    Sequential Redundancy Identification Using Verification Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:197-205 [Conf]
  112. Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote
    A Unified Framework for Design Validation and Manufacturing Test. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:875-884 [Conf]
  113. Ashwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee
    Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:252-261 [Conf]
  114. William A. Rogers, Jacob A. Abraham
    CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:710-716 [Conf]
  115. Jeongjin Roh, Jacob A. Abraham
    Subband filtering scheme for analog and mixed-signal circuit testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:221-229 [Conf]
  116. Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra
    Formal Verification of a System-on-Chip Using Computation Slicing. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:810-819 [Conf]
  117. Jian Shen, Jacob A. Abraham
    Native mode functional test generation for processors with applications to self test and design validation. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:990-999 [Conf]
  118. Kurt H. Thearling, Jacob A. Abraham
    An Easily Computed Functional Level Testability Measure. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:381-390 [Conf]
  119. Raghuram S. Tupuri, Jacob A. Abraham
    A Novel Functional Test Generation Method for Processors Using Commercial ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:743-752 [Conf]
  120. Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab
    CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:606-615 [Conf]
  121. Hak-soo Yu, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham
    Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1389-1397 [Conf]
  122. Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham
    On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:31-37 [Conf]
  123. Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham
    On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:103-109 [Conf]
  124. Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri
    Delay Constrained Register Transfer Level Dynamic Power Estimation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:36-46 [Conf]
  125. Prithviraj Banerjee, Jacob A. Abraham
    A Probabilistic Model of Algorithm-Based Fault Tolerance in Array Processors for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1986, pp:72-78 [Conf]
  126. Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham
    Design of a scalable parallel switch-level simulator for VLSI. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:615-624 [Conf]
  127. W. Kent Fuchs, Kun-Lung Wu, Jacob A. Abraham
    Low-Cost Comparison and Diagnosis of Large Remotely Located Files. [Citation Graph (0, 0)][DBLP]
    Symposium on Reliability in Distributed Software and Database Systems, 1986, pp:67-73 [Conf]
  128. Jacob A. Abraham, Gopi Ganapathy
    Practical Test and DFT for Next Generation VLSI. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:3- [Conf]
  129. Pradip Bose, Jacob A. Abraham
    Performance and Functional Verification of Microprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:58-63 [Conf]
  130. Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell
    Verification of Circuits Described in VHDL through Extraction of Design Intent. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:417-420 [Conf]
  131. Sankaran Karthik, Jacob A. Abraham, Raymond P. Voith
    Optimizations for Behavioral/RTL Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:311-316 [Conf]
  132. Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross
    Efficient variable ordering and partial representation algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:81-86 [Conf]
  133. Rathish Jayabharathi, Manuel A. d'Abreu, Jacob A. Abraham
    FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:232-235 [Conf]
  134. Arun Krishnamachary, Jacob A. Abraham
    Effects of Multi-cycle Sensitization on Delay Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:137-142 [Conf]
  135. Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri
    Timing Verification and Delay Test Generation for Hierarchical Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:157-162 [Conf]
  136. Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
    Towards The Complete Elimination of Gate/Switch Level Simulations. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:115-0 [Conf]
  137. Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
    On More Efficient Combinational ATPG Using Functional Learning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:107-110 [Conf]
  138. Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
    Efficient multisine testing of analog circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:234-238 [Conf]
  139. Hak-soo Yu, Jacob A. Abraham
    An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:441-446 [Conf]
  140. Qiang Qiang, Daniel G. Saab, Jacob A. Abraham
    Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:225-230 [Conf]
  141. Jeongjin Roh, Jacob A. Abraham
    A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:572-0 [Conf]
  142. Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula
    Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:243-248 [Conf]
  143. Raghuram S. Tupuri, Jacob A. Abraham
    A Novel Hierarchical Test Generation Method for Processors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:540-541 [Conf]
  144. Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham
    Automatic Validation Test Generation Using Extracted Control Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:312-0 [Conf]
  145. Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab
    Hierarchical Test Generation for Systems On a Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:198-0 [Conf]
  146. Vivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham
    Program Slicing for ATPG-Based Property Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:591-596 [Conf]
  147. Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham
    Efficient Microprocessor Verification using Antecedent Conditioned Slicing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:43-49 [Conf]
  148. Jacob A. Abraham, Daniel G. Saab
    Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:6- [Conf]
  149. Henry Chang, Steve Dollens, Gordon Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham
    Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:415-416 [Conf]
  150. Magdy S. Abadir, Jacob A. Abraham, H. Hao, C. Hunter, Wayne M. Needham, Ron G. Walther
    Microprocessor Test and Validation: Any New Avenues? [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:458-464 [Conf]
  151. Ashok Balivada, Yatin Vasant Hoskote, Jacob A. Abraham
    Verification of transient response of linear analog circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:42-47 [Conf]
  152. Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham
    Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:354-361 [Conf]
  153. Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham
    A Scheme for On-Chip Timing Characterization. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:24-29 [Conf]
  154. Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham
    Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:275-280 [Conf]
  155. Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
    Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:9-14 [Conf]
  156. Kyung Tek Lee, Clay Nordquist, Jacob A. Abraham
    Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:34-41 [Conf]
  157. Rathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham
    A Novel Solution for Chip-Level Functional Timing Verification. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:137-142 [Conf]
  158. Dinos Moundanos, Jacob A. Abraham
    Using Verification Technology for Validation Coverage Analysis and Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:254-259 [Conf]
  159. Ashwin Raghunathan, Hongjoong Shin, Jacob A. Abraham, Abhijit Chatterjee
    Prediction of Analog Performance Parameters Using Oscillation Based Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:377-382 [Conf]
  160. Jeongjin Roh, Jacob A. Abraham
    A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:143-148 [Conf]
  161. Jian Shen, Jacob A. Abraham
    Verification of Processor Microarchitectures. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:189-194 [Conf]
  162. Hongjoong Shin, Byoungho Kim, Jacob A. Abraham
    Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:412-419 [Conf]
  163. Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra
    Program Slicing for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:237-246 [Conf]
  164. Hak-soo Yu, Sungbae Hwang, Jacob A. Abraham
    DSP-Based Statistical Self Test of On-Chip Converters. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:83-88 [Conf]
  165. Byoungho Kim, Zhenhai Fu, Jacob A. Abraham
    Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:291-296 [Conf]
  166. Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham
    A novel test generation approach for parametric faults in linear analog circuits . [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:470-475 [Conf]
  167. Kyoil Kim, Jacob A. Abraham, Jayanta Bhadra
    Model Checking of Security Protocols with Pre-configuration. [Citation Graph (0, 0)][DBLP]
    WISA, 2003, pp:1-15 [Conf]
  168. Ashok Balivada, Jin Chen, Jacob A. Abraham
    Analog Testing with Time Response Parameters. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:18-25 [Journal]
  169. Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham
    Design and Development Paradigm for Industrial Formal Verification CAD Tools. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:26-35 [Journal]
  170. Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
    Validating PowerPC Microprocessor Custom Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:61-76 [Journal]
  171. Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham
    Efficient Model Checking of Hardware Using Conditioned Slicing. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2005, v:128, n:6, pp:279-294 [Journal]
  172. Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham
    A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2005, v:27, n:1-2, pp:67-112 [Journal]
  173. Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell
    Probabilistic Verification of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1992, v:1, n:1, pp:61-115 [Journal]
  174. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita
    Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:21, n:1, pp:95-101 [Journal]
  175. Craig M. Chase, Prakash Arunachalam, Jacob A. Abraham
    Memory Distribution: Techniques and Practice for CAD Applications. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1998, v:24, n:11, pp:1597-1615 [Journal]
  176. Jacob A. Abraham
    A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:5, pp:578-584 [Journal]
  177. Jacob A. Abraham, Daniel Gajski
    Design of Testable Structures Defined by Simple Loops. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:11, pp:875-884 [Journal]
  178. Prithviraj Banerjee, Jacob A. Abraham
    Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:4, pp:296-306 [Journal]
  179. Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham
    Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:9, pp:1132-1145 [Journal]
  180. Dhananjay Brahme, Jacob A. Abraham
    Functional Testing of Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:6, pp:475-485 [Journal]
  181. Abhijit Chatterjee, Jacob A. Abraham
    The Testability of Generalized Counters Under Multiple Faulty Cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:11, pp:1378-1385 [Journal]
  182. Abhijit Chatterjee, Jacob A. Abraham
    Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:10, pp:1133-1148 [Journal]
  183. Timothy C. K. Chou, Jacob A. Abraham
    Load Redistribution Under Failure in Distributed Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:9, pp:799-808 [Journal]
  184. Timothy C. K. Chou, Jacob A. Abraham
    Distributed Control of Computer Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:6, pp:564-567 [Journal]
  185. Kuang-Hua Huang, Jacob A. Abraham
    Algorithm-Based Fault Tolerance for Matrix Operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:6, pp:518-528 [Journal]
  186. Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
    Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:11, pp:1230-1245 [Journal]
  187. Jing-Yang Jou, Jacob A. Abraham
    Fault-Tolerant FFT Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:5, pp:548-561 [Journal]
  188. Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote
    Abstraction Techniques for Validation Coverage Analysis and Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:1, pp:2-14 [Journal]
  189. V. S. S. Nair, Jacob A. Abraham
    Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:426-435 [Journal]
  190. V. S. S. Nair, Jacob A. Abraham, Prithviraj Banerjee
    Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:499-503 [Journal]
  191. V. S. S. Nair, Yatin Vasant Hoskote, Jacob A. Abraham
    Probabilistic Evaluation of On-Line Checks in Fault-Tolerant Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:5, pp:532-541 [Journal]
  192. Ravindra Nair, Satish M. Thatte, Jacob A. Abraham
    Efficient Algorithms for Testing Semiconductor Random-Access Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:6, pp:572-576 [Journal]
  193. Satish M. Thatte, Jacob A. Abraham
    Test Generation for Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:6, pp:429-441 [Journal]
  194. Prithviraj Banerjee, Jacob A. Abraham
    A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:312-321 [Journal]
  195. Abhijit Chatterjee, Jacob A. Abraham
    On the C-Testability of Generalized Counters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:713-726 [Journal]
  196. Niraj K. Jha, Jacob A. Abraham
    Design of Testable CMOS Logic Circuits Under Arbitrary Delays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:264-269 [Journal]
  197. Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos
    Automatic verification of implementations of large circuits against HDL specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:217-228 [Journal]
  198. Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham
    Test compaction for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:2, pp:260-267 [Journal]
  199. Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
    VLSI logic and fault simulation on general-purpose parallel computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:446-460 [Journal]
  200. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
    An efficient filter-based approach for combinational verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1542-1557 [Journal]
  201. Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham
    Signature analysis for analog and mixed-signal circuit test response compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:540-546 [Journal]
  202. William A. Rogers, John F. Guzolek, Jacob A. Abraham
    Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:848-862 [Journal]
  203. Jeongjin Roh, Jacob A. Abraham
    A comprehensive signature analysis scheme for oscillation-test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1409-1423 [Journal]
  204. Daniel G. Saab, Youssef Saab, Jacob A. Abraham
    Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1278-1285 [Journal]
  205. Hsi-Ching Shih, Joseph T. Rahmeh, Jacob A. Abraham
    FAUST: An MOS Fault Simulator with Timing Information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:557-563 [Journal]
  206. Zeyad Alkhalifa, V. S. S. Nair, Narayanan Krishnamurthy, Jacob A. Abraham
    Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:6, pp:627-641 [Journal]
  207. Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham
    Benchmarking Parallel Processing Platforms: An Applications Perspective. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:8, pp:947-954 [Journal]
  208. W. Kent Fuchs, Kun-Lung Wu, Jacob A. Abraham
    Comparison and Diagnosis of Large Replicated Files. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1987, v:13, n:1, pp:15-22 [Journal]
  209. Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu
    Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2006, pp:71-80 [Conf]
  210. Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham
    Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:199-204 [Conf]
  211. Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab
    Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:173-178 [Conf]
  212. Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham
    Improved verification of hardware designs through antecedent conditioned slicing. [Citation Graph (0, 0)][DBLP]
    STTT, 2007, v:9, n:1, pp:89-101 [Journal]
  213. Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham
    Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:10, pp:1401-1414 [Journal]
  214. Marc E. Levitt, Kaushik Roy, Jacob A. Abraham
    BiCMOS logic testing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:241-248 [Journal]
  215. Sungbae Hwang, Jacob A. Abraham
    Test data compression and test time reduction using an embedded microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:853-862 [Journal]

  216. Analytical model for the impact of multiple input switching noise on timing. [Citation Graph (, )][DBLP]


  217. LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits. [Citation Graph (, )][DBLP]


  218. A Random Jitter RMS Estimation Technique for BIST Applications. [Citation Graph (, )][DBLP]


  219. A low-cost concurrent error detection technique for processor control logic. [Citation Graph (, )][DBLP]


  220. Implications of Technology Trends on System Dependability. [Citation Graph (, )][DBLP]


  221. SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000. [Citation Graph (, )][DBLP]


  222. High level test generation using data flow descriptions. [Citation Graph (, )][DBLP]


  223. Derivation of signal flow for switch-level simulation. [Citation Graph (, )][DBLP]


  224. On efficient generation of instruction sequences to test for delay defects in a processor. [Citation Graph (, )][DBLP]


  225. A delay measurement method using a shrinking clock signal. [Citation Graph (, )][DBLP]


  226. A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA. [Citation Graph (, )][DBLP]


  227. Adaptive SRAM memory for low power and high yield. [Citation Graph (, )][DBLP]


  228. Efficient parallel algorithms for processor arrays. [Citation Graph (, )][DBLP]


  229. Using write back cache to improve performance of multi-user multiprocessors. [Citation Graph (, )][DBLP]


  230. Error detection in 2-D Discrete Wavelet lifting transforms. [Citation Graph (, )][DBLP]


  231. Budget-Dependent Control-Flow Error Detection. [Citation Graph (, )][DBLP]


  232. Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. [Citation Graph (, )][DBLP]


  233. Characterization of Standard Cells for Intra-Cell Mismatch Variations. [Citation Graph (, )][DBLP]


  234. Cache Design for Low Power and High Yield. [Citation Graph (, )][DBLP]


  235. Characterization of sequential cells for constraint sensitivities. [Citation Graph (, )][DBLP]


  236. Functionally valid gate-level peak power estimation for processors. [Citation Graph (, )][DBLP]


  237. Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM. [Citation Graph (, )][DBLP]


  238. A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. [Citation Graph (, )][DBLP]


  239. Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. [Citation Graph (, )][DBLP]


  240. Parallel Loopback Test of Mixed-Signal Circuits. [Citation Graph (, )][DBLP]


  241. Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits. [Citation Graph (, )][DBLP]


  242. Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors. [Citation Graph (, )][DBLP]


  243. Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems. [Citation Graph (, )][DBLP]


  244. Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. [Citation Graph (, )][DBLP]


  245. A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. [Citation Graph (, )][DBLP]


  246. Calibration-enabled scalable built-in current sensor compatible with very low cost ATE. [Citation Graph (, )][DBLP]


  247. Critical Path Selection for Delay Test Considering Coupling Noise. [Citation Graph (, )][DBLP]


  248. A timing methodology considering within-die clock skew variations. [Citation Graph (, )][DBLP]


Search in 0.011secs, Finished in 0.918secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002