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Alvin M. Despain: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alvin M. Despain, David A. Patterson
    X-Tree: A Tree Structured Multi-Processor Computer Architecture. [Citation Graph (2, 0)][DBLP]
    ISCA, 1978, pp:144-151 [Conf]
  2. Hervé J. Touati, Alvin M. Despain
    An Empirical Study of the Warren Abstract Machine. [Citation Graph (2, 0)][DBLP]
    SLP, 1987, pp:114-124 [Conf]
  3. Saul Amarel, Alvin M. Despain, H. Penny Nii, Louis I. Steinberg, Marty Tenenbaum, Peter M. Will
    AI and Design. [Citation Graph (1, 0)][DBLP]
    IJCAI, 1991, pp:563-568 [Conf]
  4. Jung-Herng Chang, Alvin M. Despain
    Semi-Intelligent Backtracking of Prolog Based on Static Data Dependency Analysis. [Citation Graph (1, 0)][DBLP]
    SLP, 1985, pp:10-21 [Conf]
  5. Peter Van Roy, Alvin M. Despain
    High-Performance Logic Programming with the Aquarius Prolog Compiler. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1992, v:25, n:1, pp:54-68 [Journal]
  6. Carlo H. Séquin, Alvin M. Despain, David A. Patterson
    Communication In X-TREE, A Modular Multiprocessor System. [Citation Graph (0, 0)][DBLP]
    ACM Annual Conference (1), 1978, pp:194-203 [Conf]
  7. Jung-Herng Chang, Alvin M. Despain, Doug DeGroot
    AND-Parallelism of Logic Programs Based on a Static Data Dependency Analysis. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1985, pp:218-226 [Conf]
  8. Alvin M. Despain
    Prolog at Berkeley. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1988, pp:64-67 [Conf]
  9. Alvin M. Despain, Yale N. Patt
    The Aquarius Project. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1984, pp:364-368 [Conf]
  10. Alvin M. Despain, Yale N. Patt
    Aquarius - A High Performance Computing System for Symbolic/Numeric Applications. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1985, pp:376-382 [Conf]
  11. Alvin M. Despain, Yale N. Patt, Tep P. Dobry, Jung-Herng Chang, Wayne Citrin
    High Performance Prolog, The Multiplicative Effect of Several Levels of Implementation. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1986, pp:178-185 [Conf]
  12. Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain
    Lower Power Architecture Design and Compilation Techniques for High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    COMPCON, 1994, pp:489-498 [Conf]
  13. Ing-Jer Huang, Alvin M. Despain
    High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:135-140 [Conf]
  14. Ing-Jer Huang, Alvin M. Despain
    Synthesis of Instruction Sets for Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:5-11 [Conf]
  15. Shihming Liu, Massoud Pedram, Alvin M. Despain
    A Fast State Assignment Procedure for Large FSMs. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:327-332 [Conf]
  16. Jonathan D. Pincus, Alvin M. Despain
    Delay reduction using simulated annealing. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:690-695 [Conf]
  17. Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain
    Application-Driven Design Automation for Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:512-517 [Conf]
  18. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Technology Decomposition and Mapping Targeting Low Power Dissipation. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:68-73 [Conf]
  19. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:18-23 [Conf]
  20. Ching-Long Su, Alvin M. Despain
    Cache designs for energy efficiency. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:306-315 [Conf]
  21. Ing-Jer Huang, Alvin M. Despain
    Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:594-599 [Conf]
  22. Ing-Jer Huang, Alvin M. Despain
    Generating instruction sets and microarchitectures from applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:391-396 [Conf]
  23. Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain
    Low power state assignment targeting two-and multi-level logic implementations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:82-87 [Conf]
  24. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Efficient estimation of dynamic power consumption under a real delay model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:224-228 [Conf]
  25. Ching-Long Su, Chin-Chi Teng, Alvin M. Despain
    A Study of Cache Hashing Functions for Symbolic Applications in Micro-Parallel Processors. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:530-537 [Conf]
  26. Tam M. Nguyen, Vason P. Srini, Alvin M. Despain
    A two-tier memory architecture for high-performance multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    ICS, 1988, pp:326-336 [Conf]
  27. Darren R. Busing, Vason P. Srini, Georges E. Smine, Michael J. Carlton, Alvin M. Despain
    The Aquarius IIU System. [Citation Graph (0, 0)][DBLP]
    ICSI, 1990, pp:38-46 [Conf]
  28. Won Woo Ro, Jean-Luc Gaudiot, Stephen P. Crago, Alvin M. Despain
    HiDISC: A Decoupled Architecture for Data-Intensive Application. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:3- [Conf]
  29. Philip Bitar, Alvin M. Despain
    Multiprocessor Cache Synchronization: Issues, Innovations, Evolution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:424-433 [Conf]
  30. Tep P. Dobry, Alvin M. Despain, Yale N. Patt
    Performance Studies of a Prolog Machine Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:180-190 [Conf]
  31. Barry S. Fagin, Alvin M. Despain
    Performance Studies of a Parallel Prolog Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:108-116 [Conf]
  32. Ching-Long Su, Alvin M. Despain
    Branch with Masked Squashing in Superpipelined Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:130-140 [Conf]
  33. Bruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Ralph Clarke Haygood, William R. Bush, Alvin M. Despain, Joan M. Pendleton, Tep P. Dobry
    Fast Prolog with an Extended General Purpose Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:282-291 [Conf]
  34. Shihming Liu, Massoud Pedram, Alvin M. Despain
    PLATO P: PLA Timing Optimization by Partitioning. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1744-1747 [Conf]
  35. Apoorv Srivastava, Yong-Seon Koh, Barton Sano, Alvin M. Despain
    190-MHz CMOS 4-Kbyte Pipelined Caches. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1053-1056 [Conf]
  36. Ching-Long Su, Alvin M. Despain
    Cache design trade-offs for power and performance optimization: a case study. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:63-68 [Conf]
  37. Ching-Long Su, Alvin M. Despain
    Minimizing branch misprediction penalties for superpipelined processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:138-142 [Conf]
  38. Ing-Jer Huang, Alvin M. Despain
    An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:236-246 [Conf]
  39. Bruce K. Holmer, Alvin M. Despain
    Viewing Instruction Set Design as an Optimization Problem. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:153-162 [Conf]
  40. Barton Sano, Alvin M. Despain
    The 16-fold way: a microparallel taxonomy. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:60-69 [Conf]
  41. Apoorv Srivastava, Alvin M. Despain
    Prophetic branches: a branch architecture for code compaction and efficient execution. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:94-99 [Conf]
  42. Kevin M. Obenland, Alvin M. Despain
    Simulating the Effect of Decoherence and Inaccuracies on a Quantum Computer. [Citation Graph (0, 0)][DBLP]
    QCQC, 1998, pp:447-459 [Conf]
  43. William R. Bush, Gino Cheng, Patrick C. McGeer, Alvin M. Despain
    Experience with Prolog as a Hardware Specification Language. [Citation Graph (0, 0)][DBLP]
    SLP, 1987, pp:490-498 [Conf]
  44. Peter Van Roy, Alvin M. Despain
    The Benefits of Global Dataflow Analysis for an Optimizing Prolog Compiler. [Citation Graph (0, 0)][DBLP]
    NACLP, 1990, pp:501-515 [Conf]
  45. Alvin M. Despain, Robert Yung
    An integrated prolog architecture for symbolic and numeric executions. [Citation Graph (0, 0)][DBLP]
    Ann. Math. Artif. Intell., 1991, v:4, n:, pp:107-133 [Journal]
  46. Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain
    Scalable Shared-Memory Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1990, v:23, n:6, pp:71-83 [Journal]
  47. Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain
    Saving Power in the Control Path of Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:4, pp:24-30 [Journal]
  48. Shihming Liu, Massoud Pedram, Alvin M. Despain
    State assignment based on two-dimensional placement and hypercube mapping. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:24, n:2, pp:101-118 [Journal]
  49. Bruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Alvin M. Despain
    Design and Analysis of Hardware for High-Performance Prolog. [Citation Graph (0, 0)][DBLP]
    J. Log. Program., 1996, v:29, n:1-3, pp:107-139 [Journal]
  50. Vason P. Srini, Tam M. Nguyen, Darren R. Busing, Michael J. Carlton, Bruce K. Holmer, Georges E. Smine, Alvin M. Despain
    Design and Simulation of the Aquarius-II Multiprocessor. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Integration, 1997, v:7, n:2, pp:151-178 [Journal]
  51. Alvin M. Despain
    Very Fast Fourier Transform Algorithms Hardware for Implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:5, pp:333-341 [Journal]
  52. Barry S. Fagin, Alvin M. Despain
    The Performance of Parallel Prolog Programs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:12, pp:1434-1445 [Journal]
  53. Erling Wold, Alvin M. Despain
    Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:5, pp:414-426 [Journal]
  54. Ing-Jer Huang, Alvin M. Despain
    Synthesis of application specific instruction sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:663-675 [Journal]
  55. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Power efficient technology decomposition and mapping under an extended power consumption model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1110-1122 [Journal]
  56. Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
    Low-power state assignment targeting two- and multilevel logic implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:12, pp:1281-1291 [Journal]
  57. Won Woo Ro, Stephen P. Crago, Alvin M. Despain, Jean-Luc Gaudiot
    Design and evaluation of a hierarchical decoupled architecture. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:38, n:3, pp:237-259 [Journal]
  58. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Power estimation methods for sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:404-416 [Journal]
  59. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:495- [Journal]

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