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Stephen Y. H. Su: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Li Shen, Stephen Y. H. Su
    VLSI functional testing using critical path traces at hardware description language level. [Citation Graph (0, 0)][DBLP]
    Fehlertolerierende Rechensysteme, 1984, pp:364-379 [Conf]
  2. Chi-Chang Liaw, Stephen Y. H. Su
    A New Fault Model and Testing Technique for CMOS Devices. [Citation Graph (0, 0)][DBLP]
    ITC, 1982, pp:25-34 [Conf]
  3. Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya
    State Diagram Approach for Functional Testing of Control Section. [Citation Graph (0, 0)][DBLP]
    ITC, 1981, pp:433-446 [Conf]
  4. Tonysheng Lin, Stephen Y. H. Su
    Functional Test Generation of Digital LSI/VLSI Systems Using Machine Symbolic Execution Technique. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:660-668 [Conf]
  5. Tonysheng Lin, Stephen Y. H. Su
    VLSI Functional Test Pattern Generation: A Design and Implementation. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:922-929 [Conf]
  6. Stephen Y. H. Su, Yu-I Hsieh
    Testing Functional Faults in Digital Systems Described by Register Transfer Language. [Citation Graph (0, 0)][DBLP]
    ITC, 1981, pp:447-457 [Conf]
  7. Stephen Y. H. Su, Hede Ma
    Fault Isolation in Grey Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:54-63 [Conf]
  8. Kewal K. Saluja, Li Shen, Stephen Y. H. Su
    A Simplified Algorithm for Testing Microprocessors. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:668-675 [Conf]
  9. Stephen Y. H. Su, Hede Ma
    Designs for Diagnosability and Reliability in VLSI Systems. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:888-897 [Conf]
  10. Stephen Y. H. Su, Rong Yao
    Fault-Tolerant Array Processors Via Reconfiguration of Two-Level Redundancy Arrays. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1997, pp:1633-1642 [Conf]
  11. Melvin A. Breuer, Shih-Jeh Chang, Stephen Y. H. Su
    Identification of Multiple Stuck-Type Faults in Combinational Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:1, pp:44-54 [Journal]
  12. Yacoub M. El-Ziq, Stephen Y. H. Su
    Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:10, pp:911-923 [Journal]
  13. Yacoub M. El-Ziq, Stephen Y. H. Su
    Fault Diagnosis of MOS Combinational Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:2, pp:129-139 [Journal]
  14. Mark G. Karpovsky, Stephen Y. H. Su
    Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:6, pp:523-527 [Journal]
  15. Israel Koren, Zahava Koren, Stephen Y. H. Su
    Analaysis of a Class of Recovery Procedures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:8, pp:703-712 [Journal]
  16. Israel Koren, Stephen Y. H. Su
    Reliability Analysis of N-Modular Redundancy Systems with Intermittent and Permanent Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:7, pp:514-520 [Journal]
  17. Chi-Chang Liaw, Stephen Y. H. Su, Yashwant K. Malaiya
    Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:12, pp:989-995 [Journal]
  18. Yashwant K. Malaiya, Stephen Y. H. Su
    Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:8, pp:600-604 [Journal]
  19. Stephen Y. H. Su, Edgar DuCasse
    A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:3, pp:254-258 [Journal]
  20. Li Shen, Stephen Y. H. Su
    A Functional Testing Method for Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:10, pp:1288-1293 [Journal]
  21. Richard J. Spillman, Stephen Y. H. Su
    Detection of Single, Stuck-Type Faulures in Multivalued Combinational Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:12, pp:1242-1251 [Journal]
  22. Stephen Y. H. Su, Michal Cutler, Mingshien Wang
    Self-Diagnosis of Faelures in VLSI Tree Array Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:11, pp:1252-1257 [Journal]
  23. Stephen Y. H. Su, Israel Koren, Yashwant K. Malaiya
    A Continous-Parameter Markov Model and Detection Procedures for Intermittent Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:6, pp:567-570 [Journal]
  24. Mingshien Wang, Michal Cutler, Stephen Y. H. Su
    Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:4, pp:547-554 [Journal]
  25. Shiyi Xu, Stephen Y. H. Su
    Detecting I/O and Internal Feedback Bridging Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:6, pp:553-557 [Journal]
  26. Tonysheng Lin, Stephen Y. H. Su
    The S-Algorithm: A Promising Solution for Systematic Functional Test Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:250-263 [Journal]

  27. An overview of fault-tolerant digital system architecture. [Citation Graph (, )][DBLP]


  28. IDAS: an integrated design automation system. [Citation Graph (, )][DBLP]


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