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Donald E. Thomas :
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Donald E. Thomas Observations on comparing digital systems synthesis techniques. [Citation Graph (0, 0)][DBLP ] ACM Conference on Computer Science, 1985, pp:17-22 [Conf ] JoAnn M. Paul , Christopher M. Eatedali , Donald E. Thomas The design context of concurrent computation systems. [Citation Graph (0, 0)][DBLP ] CODES, 2002, pp:19-24 [Conf ] JoAnn M. Paul , Simon N. Peffers , Donald E. Thomas Frequency interleaving as a codesign scheduling paradigm. [Citation Graph (0, 0)][DBLP ] CODES, 2000, pp:131-135 [Conf ] JoAnn M. Paul , Donald E. Thomas , Alex Bobrek Benchmark-based design strategies for single chip heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP ] CODES+ISSS, 2004, pp:54-59 [Conf ] Donald E. Thomas , JoAnn M. Paul , Simon N. Peffers , Sandra J. Weber Peer-based multithreaded executable co-specification. [Citation Graph (0, 0)][DBLP ] CODES, 1999, pp:105-109 [Conf ] Neal K. Tibrewala , JoAnn M. Paul , Donald E. Thomas Modeling and evaluation of hardware/software designs. [Citation Graph (0, 0)][DBLP ] CODES, 2001, pp:11-16 [Conf ] Jay K. Adams , Donald E. Thomas The Design of Mixed Hardware/Software Systems. [Citation Graph (0, 0)][DBLP ] DAC, 1996, pp:515-520 [Conf ] Lawrence F. Arnstein , Donald E. Thomas The Attributed-Behavior Abstraction and Synthesis Tools. [Citation Graph (0, 0)][DBLP ] DAC, 1994, pp:557-561 [Conf ] Robert L. Blackburn , Donald E. Thomas , Patti M. Koenig CORAL II: Linking Behavior and Structure in an IC Design System. [Citation Graph (0, 0)][DBLP ] DAC, 1988, pp:529-535 [Conf ] Richard J. Cloutier , Donald E. Thomas The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:71-76 [Conf ] Richard J. Cloutier , Donald E. Thomas Synthesis of Pipelined Instruction Set Processors. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:583-588 [Conf ] William E. Dougherty , Donald E. Thomas Unifying behavioral synthesis and physical design. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:756-761 [Conf ] Christopher Inacio , Herman Schmit , David Nagle , Andrew Ryan , Donald E. Thomas , Yingfai Tong , Ben Klass Vertical Benchmarks for CAD. [Citation Graph (0, 0)][DBLP ] DAC, 1999, pp:408-413 [Conf ] Elizabeth D. Lagnese , Donald E. Thomas Architectural Partitioning for System Level Design. [Citation Graph (0, 0)][DBLP ] DAC, 1989, pp:62-67 [Conf ] JoAnn M. Paul , Simon N. Peffers , Donald E. Thomas A codesign virtual machine for hierarchical, balanced hardware/software system modeling. [Citation Graph (0, 0)][DBLP ] DAC, 2000, pp:390-395 [Conf ] JoAnn M. Paul , Alex Bobrek , Jeffrey E. Nelson , Joshua J. Pieper , Donald E. Thomas Schedulers as model-based design elements in programmable heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:408-411 [Conf ] Joshua J. Pieper , Alain Mellan , JoAnn M. Paul , Donald E. Thomas , Faraydon Karim High level cache simulation for heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:287-292 [Conf ] Prashant Sawkar , Donald E. Thomas Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:368-373 [Conf ] Prashant Sawkar , Donald E. Thomas Performance Directed Technology Mapping for Look-Up Table Based FPGAs. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:208-212 [Conf ] Prashant Sawkar , Donald E. Thomas Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs. [Citation Graph (0, 0)][DBLP ] DAC, 1995, pp:201-205 [Conf ] Donald E. Thomas , Elizabeth M. Dirkes , Robert A. Walker , Jayanth V. Rajan , John A. Nestor , Robert L. Blackburn The System Architect's Workbench. [Citation Graph (0, 0)][DBLP ] DAC, 1988, pp:337-343 [Conf ] Thaddeus J. Kowalski , Donald E. Thomas The VLSI design automation assistant: what's in a knowledge base. [Citation Graph (0, 0)][DBLP ] DAC, 1985, pp:252-258 [Conf ] Robert A. Walker , Donald E. Thomas A model of design representation and synthesis. [Citation Graph (0, 0)][DBLP ] DAC, 1985, pp:453-459 [Conf ] Jayanth V. Rajan , Donald E. Thomas Synthesis by delayed binding of decisions. [Citation Graph (0, 0)][DBLP ] DAC, 1985, pp:367-373 [Conf ] Robert L. Blackburn , Donald E. Thomas Linking the behavioral and structural dominis of representation in a synthesis system. [Citation Graph (0, 0)][DBLP ] DAC, 1985, pp:374-380 [Conf ] Alex Bobrek , Joshua J. Pieper , Jeffrey E. Nelson , JoAnn M. Paul , Donald E. Thomas Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. [Citation Graph (0, 0)][DBLP ] DATE, 2004, pp:1144-1149 [Conf ] Andrew S. Cassidy , JoAnn M. Paul , Donald E. Thomas Layered, Multi-Threaded, High-Level Performance Design. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:10954-10959 [Conf ] JoAnn M. Paul , Donald E. Thomas A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. [Citation Graph (0, 0)][DBLP ] DATE, 2002, pp:522-528 [Conf ] Herman Schmit , Donald E. Thomas Hidden Markov modeling and fuzzy controllers in FPGAs. [Citation Graph (0, 0)][DBLP ] FCCM, 1995, pp:214-221 [Conf ] Srihari Cadambi , Jeffrey Weener , Seth Copen Goldstein , Herman Schmit , Donald E. Thomas Managing Pipeline-Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] FPGA, 1998, pp:55-64 [Conf ] Lawrence F. Arnstein , Donald E. Thomas A general consistency technique for increasing the controllability of high level synthesis tools. [Citation Graph (0, 0)][DBLP ] ICCAD, 1993, pp:741-744 [Conf ] Herman Schmit , Donald E. Thomas Address generation for memories containing multiple arrays. [Citation Graph (0, 0)][DBLP ] ICCAD, 1995, pp:510-514 [Conf ] D. L. Springer , Donald E. Thomas Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] ICCAD, 1990, pp:254-257 [Conf ] Jay K. Adams , John Alan Miller , Donald E. Thomas Execution-time profiling for multiple-process behavioral synthesis. [Citation Graph (0, 0)][DBLP ] ICCD, 1995, pp:144-149 [Conf ] Jay K. Adams , Donald E. Thomas Addressing the Tradeoff Between Standard and Custom ICs in System Level Design. [Citation Graph (0, 0)][DBLP ] ICCD, 1992, pp:194-197 [Conf ] Sari L. Coumeri , Donald E. Thomas An Environment for Exploring Low Power Memory Configurations in System Level Design. [Citation Graph (0, 0)][DBLP ] ICCD, 1999, pp:348-353 [Conf ] JoAnn M. Paul , Arne J. Suppé , Henele I. Adams , Donald E. Thomas Multi-Level Modeling of Software on Hardware in Concurrent Computation. [Citation Graph (0, 0)][DBLP ] IPDPS, 2002, pp:- [Conf ] Sari L. Coumeri , Donald E. Thomas Memory modeling for system synthesis. [Citation Graph (0, 0)][DBLP ] ISLPED, 1998, pp:179-184 [Conf ] William E. Dougherty , Donald E. Thomas Modeling and automating selection of guarding techniques for datapath elements. [Citation Graph (0, 0)][DBLP ] ISLPED, 1999, pp:182-187 [Conf ] Andrew S. Cassidy , Christopher P. Andrews , Donald E. Thomas , JoAnn M. Paul System-Level Modeling of a Network Switch SoC. [Citation Graph (0, 0)][DBLP ] ISSS, 2002, pp:62-67 [Conf ] Herman Schmit , Donald E. Thomas Array mapping in behavioral synthesis. [Citation Graph (0, 0)][DBLP ] ISSS, 1995, pp:90-95 [Conf ] JoAnn M. Paul , Arne J. Suppé , Donald E. Thomas Modeling and simulation of steady state and transient behaviors for emergent SoCs. [Citation Graph (0, 0)][DBLP ] ISSS, 2001, pp:262-267 [Conf ] Jay K. Adams , Donald E. Thomas Multiple-process behavioral synthesis for mixed hardware-software systems. [Citation Graph (0, 0)][DBLP ] ISSS, 1995, pp:10-15 [Conf ] R. S. Ramchandani , Donald E. Thomas Behavioral-Test Generation using Mixed-Integer Non-linear Programming. [Citation Graph (0, 0)][DBLP ] ITC, 1994, pp:958-967 [Conf ] Donald E. Thomas , Charles Y. Hitchcock III , Thaddeus J. Kowalski , Jayanth V. Rajan , Robert A. Walker Automatic Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 1983, v:16, n:12, pp:59-70 [Journal ] Donald E. Thomas , Jay K. Adams , Herman Schmit A Model and Methodology for Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1993, v:10, n:3, pp:6-15 [Journal ] Donald E. Thomas , Daniel P. Siewiorek Measuring Designer Performance to Verify Design Automation Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1981, v:30, n:1, pp:48-61 [Journal ] Elizabeth D. Lagnese , Donald E. Thomas Architectural partitioning for system level synthesis of integrated circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:847-860 [Journal ] Herman Schmit , Donald E. Thomas Address generation for memories containing multiple arrays. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:377-385 [Journal ] D. L. Springer , Donald E. Thomas Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:843-856 [Journal ] Donald E. Thomas , Robert L. Blackburn , Jayanth V. Rajan Linking the Behavioral and Structural Domains of Representation for Digital System Design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:103-110 [Journal ] Donald E. Thomas , G. W. Leive Automating Technology Relative Logic Synthesis and Module Selection. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:94-105 [Journal ] Donald E. Thomas , John A. Nestor Defining and Implementing a Multilevel Design Representation with Simulation Applications. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:3, pp:135-145 [Journal ] Robert A. Walker , Donald E. Thomas Behavioral transformation for algorithmic level IC design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1115-1128 [Journal ] Philip Koopman , Howie Choset , Rajeev Gandhi , Bruce H. Krogh , Diana Marculescu , Priya Narasimhan , JoAnn M. Paul , Ragunathan Rajkumar , Daniel P. Siewiorek , Asim Smailagic , Peter Steenkiste , Donald E. Thomas , Chenxi Wang Undergraduate embedded system education at Carnegie Mellon. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2005, v:4, n:3, pp:500-528 [Journal ] JoAnn M. Paul , Donald E. Thomas , Andrew S. Cassidy High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:431-461 [Journal ] JoAnn M. Paul , Donald E. Thomas , Alex Bobrek Scenario-oriented design for single-chip heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:868-880 [Journal ] Alex Bobrek , JoAnn M. Paul , Donald E. Thomas Shared Resource Access Attributes for High-Level Contention Models. [Citation Graph (0, 0)][DBLP ] DAC, 2007, pp:720-725 [Conf ] Brett H. Meyer , Donald E. Thomas Rethinking Automated Synthesis of MPSoC Architectures. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:1-6 [Conf ] Herman Schmit , Donald E. Thomas Synthesis of application-specific memory designs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:101-111 [Journal ] Sari L. Coumeri , Donald E. Thomas Memory modeling for system synthesis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:327-334 [Journal ] Sandra J. Weber , JoAnn M. Paul , Donald E. Thomas Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:805-812 [Journal ] Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. [Citation Graph (, )][DBLP ] Event-based re-training of statistical contention models for heterogeneous multiprocessors. [Citation Graph (, )][DBLP ] Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs. [Citation Graph (, )][DBLP ] Slack allocation for yield improvement in NoC-based MPSoCs. [Citation Graph (, )][DBLP ] Search in 0.004secs, Finished in 0.458secs