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Zhi Guo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhi Guo, Kwok-Yan Lam, Siu Leung Chung, Ming Gu, Jia-Guang Sun
    Efficient Presentation of Multivariate Audit Data for Intrusion Detection of Web-Based Internet Services. [Citation Graph (0, 0)][DBLP]
    ACNS, 2003, pp:63-75 [Conf]
  2. Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
    Optimized Generation of Data-Path from C Codes for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:112-117 [Conf]
  3. Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers
    A quantitative analysis of the speedup factors of FPGAs over processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:162-170 [Conf]
  4. Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
    Techniques for synthesizing binaries to an advanced register/memory structure. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:118-124 [Conf]
  5. Zhi Guo, Betul Buyukkurt, Walid A. Najjar
    Input data reuse in compiling window operations onto reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:249-256 [Conf]
  6. Zhaofeng Ma, Xibin Zhao, Guo Zhi, Ming Gu, Jiaguang Sun
    Secure Anonymous Communication with Conditional Traceability. [Citation Graph (0, 0)][DBLP]
    NPC, 2005, pp:405-408 [Conf]
  7. Liwei Liu, Jun Yu, Zhi Guo
    A kind of stochastic duel model for guerrilla war. [Citation Graph (0, 0)][DBLP]
    European Journal of Operational Research, 2006, v:171, n:2, pp:430-438 [Journal]
  8. Zhi Guo, Walid A. Najjar
    A Compiler Intermediate Representation for Reconfigurable Fabrics. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  9. Zhi Guo, Abhishek Mitra, Walid A. Najjar
    Automation of IP Core Interface Generation for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  10. Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar
    Automatic Compilation Framework for Bloom Filter Based Intrusion Detection. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:413-418 [Conf]
  11. Betul Buyukkurt, Zhi Guo, Walid A. Najjar
    Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:401-412 [Conf]
  12. Yuren Zhou, Zhi Guo, Jun He
    On the Running Time Analysis of the (1+1) Evolutionary Algorithm for the Subset Sum Problem. [Citation Graph (0, 0)][DBLP]
    LSMS (1), 2007, pp:73-82 [Conf]
  13. Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers
    Optimized Generation of Data-Path from C Codes for FPGAs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  14. Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. [Citation Graph (, )][DBLP]

  15. The discovery of the fault location in NIGS. [Citation Graph (, )][DBLP]

  16. Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. [Citation Graph (, )][DBLP]

  17. The Satisfactory PID Regulator Design for Discrete Stochastic System. [Citation Graph (, )][DBLP]

  18. Opportunity-awaiting control strategy on rectangular target area. [Citation Graph (, )][DBLP]

  19. Variable structure multiple indices consistency control of stochastic system. [Citation Graph (, )][DBLP]

  20. The Analysis of the Unobservable Criteria on the Single Platform Bearings-Only Target Tracking System. [Citation Graph (, )][DBLP]

  21. The Distribution Function of Opportunity-awaiting Time for Random System with Objective Domain. [Citation Graph (, )][DBLP]

  22. Evolutionary Diagonal Recurrent Neural Network for Nonlinear Dynamic System Identification. [Citation Graph (, )][DBLP]

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