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Stefan Mangard: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Christoph Herbst, Elisabeth Oswald, Stefan Mangard
    An AES Smart Card Implementation Resistant to Power Analysis Attacks. [Citation Graph (0, 0)][DBLP]
    ACNS, 2006, pp:239-252 [Conf]
  2. Norbert Pramstaller, Stefan Mangard, Sandra Dominikus, Johannes Wolkerstorfer
    Efficient AES Implementations on ASICs and FPGAs. [Citation Graph (0, 0)][DBLP]
    AES Conference, 2004, pp:98-112 [Conf]
  3. Giuseppe Ateniese, Stefan Mangard
    A new approach to DNS security (DNSSEC). [Citation Graph (0, 0)][DBLP]
    ACM Conference on Computer and Communications Security, 2001, pp:86-95 [Conf]
  4. Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald
    Successfully Attacking Masked AES Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:157-171 [Conf]
  5. Thomas Popp, Stefan Mangard
    Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:172-186 [Conf]
  6. Stefan Mangard, Kai Schramm
    Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:76-90 [Conf]
  7. Stefan Mangard
    Hardware Countermeasures against DPA ? A Statistical Analysis of Their Effectiveness. [Citation Graph (0, 0)][DBLP]
    CT-RSA, 2004, pp:222-235 [Conf]
  8. Stefan Mangard, Thomas Popp, Berndt M. Gammel
    Side-Channel Leakage of Masked CMOS Gates. [Citation Graph (0, 0)][DBLP]
    CT-RSA, 2005, pp:351-365 [Conf]
  9. Elisabeth Oswald, Stefan Mangard, Christoph Herbst, Stefan Tillich
    Practical Second-Order DPA Attacks for Masked Smart Card Implementations of Block Ciphers. [Citation Graph (0, 0)][DBLP]
    CT-RSA, 2006, pp:192-207 [Conf]
  10. Elisabeth Oswald, Stefan Mangard
    Template Attacks on Masking - Resistance Is Futile. [Citation Graph (0, 0)][DBLP]
    CT-RSA, 2007, pp:243-256 [Conf]
  11. Elisabeth Oswald, Stefan Mangard, Norbert Pramstaller, Vincent Rijmen
    A Side-Channel Analysis Resistant Description of the AES S-Box. [Citation Graph (0, 0)][DBLP]
    FSE, 2005, pp:413-423 [Conf]
  12. Stefan Mangard
    A Simple Power-Analysis (SPA) Attackon Implementations of the AES Key Expansion. [Citation Graph (0, 0)][DBLP]
    ICISC, 2002, pp:343-358 [Conf]
  13. Manfred Josef Aigner, Stefan Mangard, Renato Menicocci, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
    A novel CMOS logic style with data independent power consumption. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1066-1069 [Conf]
  14. Srivaths Ravi, Stefan Mangard
    Tutorial T1: Designing Secure SoCs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:3- [Conf]
  15. Stefan Mangard, Manfred Josef Aigner, Sandra Dominikus
    A Highly Regular and Scalable AES Hardware Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:4, pp:483-491 [Journal]
  16. Stefan Tillich, Christoph Herbst, Stefan Mangard
    Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis. [Citation Graph (0, 0)][DBLP]
    ACNS, 2007, pp:141-157 [Conf]
  17. Thomas Popp, Mario Kirschbaum, Thomas Zefferer, Stefan Mangard
    Evaluation of the Masked Logic Style MDPL on a Prototype Chip. [Citation Graph (0, 0)][DBLP]
    CHES, 2007, pp:81-94 [Conf]
  18. Michael Hutter, Stefan Mangard, Martin Feldhofer
    Power and EM Attacks on Passive 13.56 MHz RFID Devices. [Citation Graph (0, 0)][DBLP]
    CHES, 2007, pp:320-333 [Conf]
  19. Manfred Josef Aigner, Stefan Mangard, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Thomas Popp, Giuseppe Scotti, Alessandro Trifiletti
    Side channel analysis resistant design flow. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  20. Thomas Popp, Stefan Mangard
    Implementation aspects of the DPA-resistant logic style MDPL. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  21. HyungSo Yoo, Christoph Herbst, Stefan Mangard, Elisabeth Oswald, Sang-Jae Moon
    Investigations of Power Analysis Attacks and Countermeasures for ARIA. [Citation Graph (0, 0)][DBLP]
    WISA, 2006, pp:160-172 [Conf]

  22. Practical Attacks on Masked Hardware. [Citation Graph (, )][DBLP]


  23. On the Duality of Probing and Fault Attacks [Citation Graph (, )][DBLP]


  24. Power Analysis Attacks and Countermeasures. [Citation Graph (, )][DBLP]


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