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Chao-Tsung Huang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
    Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 2003, pp:571-574 [Conf]
  2. Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hua Chen, Chung-Jr Lian, Liang-Gee Chen
    System analysis of VLSI architecture for motion-compensated temporal filtering. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2005, pp:992-995 [Conf]
  3. Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen
    Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1790-1793 [Conf]
  4. Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen
    Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5190-5193 [Conf]
  5. Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
    Reconfigurable discrete cosine transform processor for object-based video signal processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:353-356 [Conf]
  6. Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
    B-spline factorization-based architecture for inverse discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:829-832 [Conf]
  7. Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
    Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:565-568 [Conf]
  8. Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen
    VLSI implementation of shape-adaptive discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    VCIP, 2002, pp:655-666 [Conf]
  9. Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Liang-Gee Chen
    Level C+ data reuse scheme for motion estimation with corresponding coding orders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2006, v:16, n:4, pp:553-558 [Journal]
  10. Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
    Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:7, pp:910-920 [Journal]

  11. Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method. [Citation Graph (, )][DBLP]


  12. Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. [Citation Graph (, )][DBLP]


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