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Peter Pirsch :
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Hans-Joachim Stolberg , Martin Ohmacht , Peter Pirsch Cellular Multiprocessor Arrays with Adaptive Resource Utilization. [Citation Graph (0, 0)][DBLP ] ACPC, 1999, pp:480-489 [Conf ] Helge Kloos , Mladen Berekovic , Peter Pirsch Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen. [Citation Graph (0, 0)][DBLP ] ARCS, 1999, pp:5-14 [Conf ] Guillermo Payá Vayá , Javier Martín-Langerwerf , Piriya Taptimthong , Peter Pirsch Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler. [Citation Graph (0, 0)][DBLP ] ARCS, 2007, pp:254-267 [Conf ] Jens Peter Wittenburg , Willm Hinrichs , Martin Ohmacht , Hanno Lieske , Helge Kloos , Peter Pirsch HiPAR-DSP: Ein 1.3 GOPS Multimedia Signalprozessor. [Citation Graph (0, 0)][DBLP ] ARCS, 1999, pp:15-21 [Conf ] Mladen Berekovic , Peter Pirsch , Thorsten Selinger , Kai-Immo Wels , Carolina Miro , Anne Lafage , Christoph Heer , Giovanni Ghigo Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. [Citation Graph (0, 0)][DBLP ] ASAP, 2000, pp:15-24 [Conf ] Carsten Reuter , M. Schwiegershausen , Peter Pirsch Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP ] ASAP, 1997, pp:294-303 [Conf ] M. Schönfeld , M. Schwiegershausen , Peter Pirsch Synthesis of intermediate memories for the data supply to processor arrays. [Citation Graph (0, 0)][DBLP ] Algorithms and Parallel VLSI Architectures, 1991, pp:365-370 [Conf ] Mladen Berekovic , Peter Pirsch An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing. [Citation Graph (0, 0)][DBLP ] Computer Graphics International, 1998, pp:411-0 [Conf ] Jörg Hilgenstock , Klaus Herrmann , Jan Otterstedt , Dirk Niggemeyer , Peter Pirsch A Video Signal Processor for MIMD Multiprocessing. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:50-55 [Conf ] Jens Peter Wittenburg , Willm Hinrichs , Johannes Kneip , Martin Ohmacht , Mladen Berekovic , Hanno Lieske , Helge Kloos , Peter Pirsch Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:56-61 [Conf ] Hans-Joachim Stolberg , Mladen Berekovic , Lars Friebe , Sören Moch , Sebastian Flügel , Xun Mao , Mark Bernd Kulaczewski , Heiko Klußmann , Peter Pirsch HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. [Citation Graph (0, 0)][DBLP ] DATE, 2003, pp:20008-20013 [Conf ] Klaus Herrmann , Sören Moch , Jörg Hilgenstock , Peter Pirsch Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit. [Citation Graph (0, 0)][DBLP ] DFT, 2000, pp:105-113 [Conf ] Tien-Toan Do , Holger Kropp , Carsten Reuter , Peter Pirsch A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. [Citation Graph (0, 0)][DBLP ] FPL, 1998, pp:441-445 [Conf ] Tien-Toan Do , Holger Kropp , M. Schwiegershausen , Peter Pirsch Implementation of pipelined multipliers on Xilinx FPGAs. [Citation Graph (0, 0)][DBLP ] FPL, 1997, pp:51-60 [Conf ] Holger Kropp , Carsten Reuter , Matthias Wiege , Tien-Toan Do , Peter Pirsch An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes. [Citation Graph (0, 0)][DBLP ] FPL, 1999, pp:333-338 [Conf ] Matthias Winter , Peter Pirsch Von abstrakten Architekturtemplates zur hardwarenahen Architekturexploration. [Citation Graph (0, 0)][DBLP ] GI Jahrestagung (1), 2005, pp:458- [Conf ] Jörg Hilgenstock , Klaus Herrmann , Peter Pirsch Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1999, pp:42-45 [Conf ] P. Drews , Peter Pirsch , K. Schaper Circuit Technique for VLSI Design of a Video Codec. [Citation Graph (0, 0)][DBLP ] ICC (1), 1984, pp:250-255 [Conf ] Hans-Joachim Stolberg , Mladen Berekovic , Lars Friebe , Sören Moch , Sebastian Flügel , Mark Bernd Kulaczewski , Peter Pirsch HiBRID-SoC: a multi-core architecture for image and video applications. [Citation Graph (0, 0)][DBLP ] ICIP (3), 2003, pp:101-104 [Conf ] Hans-Joachim Stolberg , Mladen Berekovic , Peter Pirsch , H. Runge Implementing The MPEG-4 Advanced Simple Profile For Streaming Video Applications. [Citation Graph (0, 0)][DBLP ] ICME, 2001, pp:- [Conf ] Klaus Gaedke , Jens Franzen , Peter Pirsch A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic. [Citation Graph (0, 0)][DBLP ] ISCAS, 1993, pp:1583-1586 [Conf ] Peter Pirsch , W. Gehrke , R. Hoffer A Hierarchical Multiprocessor Achitecture for Video Coding Applications. [Citation Graph (0, 0)][DBLP ] ISCAS, 1993, pp:1750-1753 [Conf ] Peter Pirsch , Johannes Kneip , Karsten Rönner Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal Processor. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:562-565 [Conf ] Marco Winzker , Peter Pirsch , Jochen Reimers Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:609-612 [Conf ] Mladen Berekovic , K. Jacob , Peter Pirsch Architecture of a hardware module for MPEG-4 shape decoding. [Citation Graph (0, 0)][DBLP ] ISCAS (1), 1999, pp:157-160 [Conf ] M. Schwiegershausen , Peter Pirsch A system level design methodology for the optimization of heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP ] ISSS, 1995, pp:162-169 [Conf ] Mark Bernd Kulaczewski , Stefan Zimmerman , Erich Barke , Peter Pirsch CHIPDESIGN - A Novel Project-oriented Microelectronics Course. [Citation Graph (0, 0)][DBLP ] MSE, 2001, pp:71-72 [Conf ] Holger Kropp , Carsten Reuter , Peter Pirsch The Video and Image Processing Emulation System VIPES. [Citation Graph (0, 0)][DBLP ] International Workshop on Rapid System Prototyping, 1998, pp:170-175 [Conf ] Javier Martín-Langerwerf , Carsten Reuter , Holger Kropp , Peter Pirsch Benefits of Macro-Based Multi-FPGA Partitioning for Video Processing Applications. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2002, pp:60-65 [Conf ] Peter Pirsch , Achim Freimann , C. Klar , Jens Peter Wittenburg Processor Architectures for Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Embedded Processor Design Challenges, 2002, pp:188-206 [Conf ] Carsten Reuter , Javier Martín-Langerwerf , Hans-Joachim Stolberg , Peter Pirsch Performance Estimation of Streaming Media Applications for Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] SAMOS, 2004, pp:69-77 [Conf ] Guillermo Payá Vayá , Javier Martín-Langerwerf , Peter Pirsch RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration. [Citation Graph (0, 0)][DBLP ] SAMOS, 2005, pp:32-40 [Conf ] Xun Mao , Wei Wang , Huimin Gong , Yan L. He , Jian Lou , Lu Yu , Qingdong Yao , Peter Pirsch Highly efficient simulation environment for HDTV video decoder in VLSI design. [Citation Graph (0, 0)][DBLP ] VCIP, 2002, pp:1006-1014 [Conf ] J. Schönfeld , Peter Pirsch Single board image processing unit for vehicle guidance. [Citation Graph (0, 0)][DBLP ] VLSI, 1993, pp:151-160 [Conf ] M. Schönfeld , M. Schwiegershausen , Peter Pirsch Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays. [Citation Graph (0, 0)][DBLP ] VLSI, 1991, pp:297-306 [Conf ] Hans-Joachim Stolberg , Mladen Berekovic , Lars Friebe , Sören Moch , Mark Bernd Kulaczewski , Peter Pirsch HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. [Citation Graph (0, 0)][DBLP ] VLSI-SOC, 2003, pp:155-160 [Conf ] Peter Pirsch , Arun N. Netravali Transmission of gray level images by multilevel dither techniques. [Citation Graph (0, 0)][DBLP ] Computers & Graphics, 1983, v:7, n:1, pp:31-44 [Journal ] Mladen Berekovic , Sören Moch , Peter Pirsch A scalable, clustered SMT processor for digital signal processing. [Citation Graph (0, 0)][DBLP ] SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:62-69 [Journal ] Sören Moch , Mladen Berekovic , Hans-Joachim Stolberg , Lars Friebe , Mark Bernd Kulaczewski , A. Dehnhardt , Peter Pirsch HIBRID-SOC: a multi-core architecture for image and video applications. [Citation Graph (0, 0)][DBLP ] SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:55-61 [Journal ] Mladen Berekovic , Hans-Joachim Stolberg , Peter Pirsch Multicore system-on-chip architecture for MPEG-4 streaming video. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Circuits Syst. Video Techn., 2002, v:12, n:8, pp:688-0 [Journal ] Guillermo Payá Vayá , Javier Martín-Langerwerf , Piriya Taptimthong , Peter Pirsch Design Space Exploration of Media Processors: A Parameterized Scheduler. [Citation Graph (0, 0)][DBLP ] ICSAMOS, 2007, pp:41-49 [Conf ] Holger Flatt , Sebastian Hesselbarth , Sebastian Flügel , Peter Pirsch A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing. [Citation Graph (0, 0)][DBLP ] SAMOS, 2007, pp:241-250 [Conf ] An Enhanced DMA Controller in SIMD Processors for Video Applications. [Citation Graph (, )][DBLP ] A parallel hardware architecture for connected component labeling based on fast label merging. [Citation Graph (, )][DBLP ] RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip. [Citation Graph (, )][DBLP ] A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes. [Citation Graph (, )][DBLP ] Scalable Multi-Standard LSI Texture Encoder for MPEG and VC-1 Video Compression. [Citation Graph (, )][DBLP ] On the Benefit of Caching Traffic Flow Data in the Link Buffer. [Citation Graph (, )][DBLP ] Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures. [Citation Graph (, )][DBLP ] ChipDesign: from theory to real world. [Citation Graph (, )][DBLP ] Search in 0.007secs, Finished in 0.011secs